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| 型号： | QL6600PS672 |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 7/13页 |
| 文件大小： | 165K |
| 代理商： | QL6600PS672 |
Eclipse
TM
Family Data Sheet
7
Eclipse Family Data Sheet
multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control.
For output functions, I/O pins can be individually configured for active HIGH, active LOW, or open-
drain inverting operation. In the active HIGH and active LOW modes, the pins of all devices are fully
3.3V compliant.
When I/O pins are unused, the OE controls can be permanently disabled, allowing the output cell
register to be used for registered feedback into the logic array. I/O cell registers are controlled by clock,
clock enable, and reset signals, which can come from the regular routing resources, from one of the
global networks, or from two input pins per bank of I/O's. The CLK and RESET signals share a common
line, while the clock enables for each register can be independently controlled. Additionally the output
and enable registers will increase a device's register count. The addition of an output register will also
decrease the Tco. Since the output register does not need to drive the routing the length of the output
path is also reduced.
Extra registers add more inputs and outputs to the I/O structure. Extra routing resources are added to
connect the I/O structure to the other parts of the device.
I/O interface support is programmable on a per bank basis. There are 8 I/O banks per chip. Users can
not mix 2.5v I/O with 3.3v I/O on the same I/O bank. Figure 6 illustrates the I/O bank configurations.
Each I/O bank is independent of other I/O bank and each I/O bank has it's own VCCIO and VREF
supplies. A mixture of different I/O standards can be used on the device, however there is a limitation
as to which I/O standards can be supported within a given bank. Differential I/O can be shared with
Non-Differential I/O. There can only be one VREF and one VCCIO per bank.
Figure 6: Multiple I/O Banks
I/O Bank 0
I/O Bank 1
I/O Bank 4
I/O Bank 5
I
I
I
I
VCCIO 0
VCCIO 1
VCCIO 5
VCCIO 4
VCCIO 7
VCCIO 6
VCCIO 2
VCCIO 3
VREF 0
VREF 1
VREF 5
VREF 4
VREF 7
VREF 6
VREF 2
VREF 3
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