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参数资料
| 型号： | QL7100-5PT280M |
| 英文描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|280PIN |
| 中文描述： | 用户可编程特殊功能的ASIC |的CMOS | BGA封装| 280PIN |
| 文件页数： | 2/24页 |
| 文件大小： | 268K |
| 代理商： | QL7100-5PT280M |
2
www.quicklogic.com
2001 QuickLogic Corporation
QL7100 QuickDSP Data Sheet
2.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=1.00)
The AC Specifications, Logic Cell diagrams and waveforms are provided below.
Figure 2: QuickDSP Logic Cell
Table 1: Logic Cells
Symbol
Parameter
Propagation
delay (ns)
Logic Cells
1
tPD
Combinatorial delay: time taken by the combinatorial circuit to output
0.257
tSU
Setup time: the amount of time the synchronous input of the flip flop must be stable before
the active clock edge
0.22
thl
Hold time: the amount of time the synchronous input of the flip flop must be stable after the
active block edge
0
tCLK
Clock to out delay: the amount of time the synchronous input of the flip flop must be stable
after the active block edge
0.255
tCWHI
Clock High Time: the length of time that the clock stays high
0.46
tCWLO
Clock Low Time: the length of time that the clock stays low
0.46
tSET
Set Delay: amount of time between when the flip flop is ”set” (high)
and when Q is consequent “set” (high)
0.18
tRESET
Reset Delay: amount of time between when the flip flop is ”reset” (low) and when Q is
consequent “reset” (low)
0.09
tSW
Set Width: length of time that the SET signal remains high
(low if active low)
0.3
tRW
Reset Width: length of time that the RESET signal remains high
(low if active low)
0.3
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