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参数资料
| 型号： | QL7100-5PT280M |
| 英文描述： | USER PROGRAMMABLE SPECIAL FUNCTION ASIC|CMOS|BGA|280PIN |
| 中文描述： | 用户可编程特殊功能的ASIC |的CMOS | BGA封装| 280PIN |
| 文件页数： | 5/24页 |
| 文件大小： | 268K |
| 代理商： | QL7100-5PT280M |
QL7100 QuickDSP
TM
Data Sheet Rev A
5
QL7100 QuickDSP Data Sheet
Figure 8: QuickRAM Module
Table 4: RAM Cell Synchronous Write Timing
Symbol
Parameter
Propagation
delay (ns)
RAM Cell Synchronous Write Timing
1
TSWA
WA Setup Time to WCLK: the amount of time the WRITE ADDRESS
must be stable before the active edge of the WRITE CLOCK
0.675
THWA
WA Hold Time to WCLK: the amount of time the WRITE ADDRESS must
be stable after the active edge of the WRITE CLOCK
0
TSWD
WD Setup Time to WCLK: the amount of time the WRITE DATA must be
stable before the active edge of the WRITE CLOCK
0.654
THWD
WD Hold Time to WCLK: the amount of time the WRITE DATA must be
stable after the active edge of the WRITE CLOCK
0
TSWE
WE Setup Time to WCLK: the amount of time the WRITE ENABLE must
be stable before the active edge of the WRITE CLOCK
0.623
THWE
WE Hold Time to WCLK: the amount of time the WRITE ENABLE must
be stable after the active edge of the WRITE CLOCK
0
TWCRD
WCLK to RD (WA=RA) [5]: the amount of time between the active
WRITE CLOCK edge and the time when the data is available at RD
4.38
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