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参数资料
| 型号： | QL8150-7PT280C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| 封装： | 0.80 MM PITCH, LFBGA-280 |
| 文件页数： | 7/96页 |
| 文件大小： | 1607K |
| 代理商： | QL8150-7PT280C |
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2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
15
Dedicated Clock
There is one dedicated clock in the two larger devices of the Eclipse II Family (QL8325 and QL8250). This
clock connects to the clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired
connection and is multiplexed with the programmable clock input. The dedicated clock provides a fast global
network with low skew. Users have the ability to select either the dedicated clock or the programmable clock
(Figure 13).
Figure 13: Dedicated Clock Circuitry within Logic Cell
NOTE: For more information on the clocking capabilities of Eclipse II FPGAs, see QuickLogic Application
I/O Control and Local Hi-Drives
Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of
I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be
driven by the internal logic both as an I/O control or high drive. For I/O constrained designs, these pins can
be used for general purpose inputs. To provide more general purpose I/Os in the 208 PQFP package, the I/O
controls pins are not bonded out. The performance of these resources is presented in Table 9.
Table 9: I/O Control Network/Local High-Drive
Destination
TT, 25 C, 2.5 V
From Pad
From Array
I/O (far)
1.00 ns
1.14 ns
I/O (near)
0.63 ns
0.78 ns
Skew
0.37 ns
0.36 ns
Programmable Clock or
General Routing
Dedicated Clock
CLK
Logic Cell
相关PDF资料 |
PDF描述 |
|---|---|
| QL8150-7PT280I | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PT280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PTN280C | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PTN280I | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PTN280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL8250 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
| QL8250-6PQN208C-5691 | 制造商:QuickLogic Corporation 功能描述: |
| QL82SD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PB516 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
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