- 您现在的位置：买卖IC网 > PDF目录191950 > QS5930-66TQ (INTEGRATED DEVICE TECHNOLOGY INC) 5930 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 PDF资料下载
参数资料
| 型号： | QS5930-66TQ |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | Clock Driver |
| 英文描述： | 5930 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | QSOP-20 |
| 文件页数： | 5/6页 |
| 文件大小： | 67K |
| 代理商： | QS5930-66TQ |
5
INDUSTRIALTEMPERATURERANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
Ω
30p F
300
Ω
7.0V
OUTP UT
V DD
OUTP UT
160
Ω
68
Ω
28p F
AC TEST LOADS AND WAVEFORMS
TEST CIRCUIT 1
TEST CIRCUIT 2
SIMPLIFIED DIAGRAM OF QS5930T FEEDBACK
Q/2
Q
VCO /2
/2
PHAS E
DETECTO R
INPU T
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5930T
provides for replication of incoming SYNC clock signals. Any manipu-
lation of that signal, such as frequency multiplying, is performed by
digital logic following the PLL (see the block diagram). The key advan-
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back,
it will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system. In most applications, the output
will optimally have zero phase shift with respect to the input. In fact, the
internal loop filter on the QS5930T typically provides within 150ps of
phase shift between input and output.
tage of the PLL circuit is to provide an effective zero propagation delay
between the output and input signals. In fact, adding delay circuits in
the feedback path, ‘propagation delay’ can even be negative! A simpli-
fied schematic of the QS5930T PLL circuit is shown below:
If the user wishes to vary the phase difference (typically to compen-
sate for backplane delays), this is most easily accomplished by adding
delay circuits to the feedback path. The respective output used for
feedback will be advanced by the amount of delay in the feedback
path. All other outputs will retain their proper relationships to that output.
相关PDF资料 |
PDF描述 |
|---|---|
| QS762470-55J | 1 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQCC44 |
| QSC112.C4A0 | PHOTO TRANSISTOR DETECTOR |
| QSC114.C6A0 | PHOTO TRANSISTOR DETECTOR |
| QSD123.A4A0 | PHOTO TRANSISTOR DETECTOR |
| QSD128.A4R0 | PHOTO TRANSISTOR DETECTOR |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QS5930T | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
| QS5931-50Q | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Six Distributed-Output Clock Driver |
| QS5931-66Q | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Six Distributed-Output Clock Driver |
| QS5931-80Q | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Six Distributed-Output Clock Driver |
| QS5931Q | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SIX DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|SSOP|20PIN|PLASTIC |
发布紧急采购，3分钟左右您将得到回复。