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| 型号： | QS5LV931-80Q |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | Clock Driver |
| 英文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | QSOP-20 |
| 文件页数： | 2/8页 |
| 文件大小： | 73K |
| 代理商： | QS5LV931-80Q |
2
INDUSTRIALTEMPERATURERANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
AVDD/VDD Supply Voltage to Ground
–0.5 to +7
V
DC Input Voltage VIN
–0.5 to +5.5
V
Maximum Power Dissipation (TA = 85°C)
0.5
W
TSTG
Storage Temperature Range
–65 to +150
° C
QSOP
TOP VIEW
CAPACITANCE (TA =+25°C,f=1MHz,V
IN
= 0V)
Pins
Typ.
Max.
Unit
CIN
34
pF
COUT
45
pF
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC
I
Referenceclockinput
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher frequencies,
LOW is for lower frequencies.
FEEDBACK
I
PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output frequency
relationships. See the Frequency Selection Table for more information.
Q0 -Q4
O
Clock outputs
Q/2
O
Clock output. Matched in phase, but frequency is half the Q frequency.
OE/
RST
I
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1, outputs are
enabled.
PLL_EN
I
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug.
VDD
—
Power supply for output buffers
AVDD
—
Power supply for phase lock loop and other internal circuitries
GND
—
Ground supply for output buffers
AGND
—
Ground supply for phase lock loop and other internal circuitries
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = –40°C to +85°C, AVDD/VDD = 3.3V ± 0.3V
Symbol
Description
– 50
– 66
– 80
Units
FMAX_Q
Max Frequency, Q0 - Q4,
50
66
80
MHz
FMAX_Q/2
Max Frequency, Q/2
25
33
40
MHz
FMIN_Q
Min Frequency, Q0 - Q4
10
MHz
FMIN_Q/2
Min Frequency, Q/2
5
MHz
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
OE/RST
FEEDBACK
AVDD
AGND
SYNC
FREQ_SEL
GND
Q1
Q4
Q/2
GND
Q3
Q2
GND
PLL_EN
GND
Q1
VDD
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