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参数资料
| 型号： | QS5LV931-80Q |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | Clock Driver |
| 英文描述： | 5LV SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | QSOP-20 |
| 文件页数： | 4/8页 |
| 文件大小： | 73K |
| 代理商： | QS5LV931-80Q |
4
INDUSTRIALTEMPERATURERANGE
QS5LV931
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter (1)
Min.
Max.
Unit
tSKR
Output Skew Between Rising Edges, Q0-Q4 and Q/2 (2)
—
300
ps
tSKF
Output Skew Between Falling Edges, Q0-Q4 and Q/2 (2)
—
300
ps
tPW
Pulse Width, Q0-Q4, Q/2 outputs, 80MHz
TCY/2
0.4
TCY/2 + 0.4
ns
tJ
Cycle-to-Cycle Jitter (4)
— 0.15
0.15
ns
tPD
SYNC Input to Feedback Delay (5)
500
500
ps
tLOCK
SYNC to Phase Lock
—
10
ms
tPZH
Output Enable Time, OE/
RST LOW to HIGH (3)
014
ns
tPZL
tPHZ
Output Disable Time, OE/
RST HIGH to LOW (3)
014
ns
tPLZ
tR,tF
Output Rise/Fall Times, 0.8V ~ 2V
0.3
2
ns
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. tPD measured at device inputs at 0.5VDD, Q output at 80MHz.
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