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参数资料
| 型号： | QS74FCT2823BTQ |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | FCT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封装： | QSOP-24 |
| 文件页数： | 6/7页 |
| 文件大小： | 60K |
| 代理商： | QS74FCT2823BTQ |
6
INDUSTRIALTEMPERATURERANGE
IDTQS74FCT2823AT/BT
HIGH-SPEEDCMOSBUSINTERFACE9-BITREGISTER
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
tSU
tH
tREM
tSU
tH
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
tW
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
VOH
tPLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
tPLH
tPHL
VOL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
SWITCH
OPEN
VOL
0.3V
tPLZ
tPZL
tPZH
tPHZ
3.5V
0V
1.5V
ENABLE
DISABLE
VOH
PRESET
CLEAR
CLOCK ENABLE
ETC.
FCTL Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Enable and Disable Times
Set-Up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
SWITCH POSITION
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
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相关代理商/技术参数 |
参数描述 |
|---|---|
| QS74FCT2823BTQX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:9-Bit D-Type Flip-Flop |
| QS74FCT2823BTSO | 制造商:未知厂家 制造商全称:未知厂家 功能描述:9-Bit D-Type Flip-Flop |
| QS74FCT2823BTSOX | 制造商:未知厂家 制造商全称:未知厂家 功能描述:9-Bit D-Type Flip-Flop |
| QS74FCT2823CTP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| QS74FCT2823CTQ | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
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