参数资料
型号: R1LV1616RSD-7SI
厂商: Renesas Technology Corp.
英文描述: 16Mb superSRAM (1M wordx16bit)
中文描述: 16Mb的superSRAM(100万wordx16bit)
文件页数: 9/16页
文件大小: 122K
代理商: R1LV1616RSD-7SI
R1LV1616R Series
Rev.1.00
2004.04.13
page 9 of 16
Write Cycle
Note
1
.
t
CHZ,
t
OHZ,
t
WHZ
and
t
BHZ
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. AT any given temperature and voltage condition,
t
HZ
max is less than
t
LZ
min both for a given device and
form device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB#
going low or UB# going low .
A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#
going high or UB# going high.
t
WP
is measured from the beginning of write to the end of write.
5.
t
CW
is measured from the later of CS1# going low or CS2 going high to end of write.
6.
t
AS
is measured the address valid to the beginning of write.
7.
t
WR
is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
1,2
ns
30
0
25
0
t
WHZ
Write to output in high-Z
Write pulse width
1,2
ns
30
0
25
0
t
OHZ
Output disable to output in high-Z
2
ns
-
5
-
5
t
OW
Output active from end of write
ns
-
0
-
0
t
DH
Data hold from write time
ns
-
40
-
35
t
DW
Data to write time overlap
7
ns
-
0
-
0
t
WR
Write recovery time
6
ns
-
0
-
0
t
AS
Address setup time
ns
-
70
-
65
t
BW
LB#,UB# valid to end of write
4
ns
-
60
-
55
t
WP
5
ns
-
70
-
65
t
CW
Chip selection to end of write
ns
-
70
-
65
t
AW
Address valid to end of write
ns
-
85
-
70
t
WC
Write cycle time
Max.
Min.
Max.
Min.
Notes
Unit
R1LV1616R**-8S
R1LV1616R**-7S
Symbol
Parameter
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