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参数资料
| 型号： | R1Q2A3618ABG-40R |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | 36-Mbit QDR™II SRAM 2-word Burst |
| 文件页数： | 15/25页 |
| 文件大小： | 394K |
| 代理商： | R1Q2A3618ABG-40R |
R1Q2A3636/R1Q2A3618/R1Q2A3609
Timing Waveforms
Read and Write Timing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
K
Q00
Q01
Q20
Q21
Q40
Q41
Q60
Q61
tKHDX
tDVKH
tKHDX
tDVKH
/K
/R
/W
Address
Data in
tCHQV
-tCHQX
tCHQV
-tCHQX
tCQHQV
-tCQHQX
-tCHQX1
tCHQZ
tCHCQV
-tCHCQX
tCHCQV
-tCHCQX
tKHKH
tKHKL
tKLKH
tKH/KH
t/KHKH
tKHKH
tKHKL
tKLKH
tKH/KH
t/KHKH
tKHCH
tKHCH
Data out
CQ
/CQ
C
/C
tKHAX
tAVKH
tKHIX
tIVKH
READ
WRITE
NOP
NOP
READ
WRITE
READ
WRITE
NOP
WRITE
READ
WRITE
NOP
NOP
NOP
NOP
tKHIX
tIVKH
A2
A1
A4
A3
A5
A7
A6
A8
D10
D11
D30
D31
D50
D51
D70
D71
D80
D81
A0
Notes: 1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following
A0, i.e., A0+1.
2. Outputs are disable (high-Z) one clock cycle after a NOP.
3. In this example, if address A0 = A1, then data Q00 = D10, Q01 = D11. Write data is forwarded immediately
as read results.
4. To control read and write operations, /BW signals must operate at the same timing as Data in.
REJ03C0294-0003 Rev.0.03 Jul. 31, 2007
Page 15 of 23
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PDF描述 |
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| R1Q2A3618ABG-50R | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3618ABG-60R | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3636 | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3636ABG-40R | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3636ABG-50R | 36-Mbit QDR™II SRAM 2-word Burst |
相关代理商/技术参数 |
参数描述 |
|---|---|
| R1Q2A3618ABG40RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3618ABG40RS0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3618ABG40RT0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3618ABG-50R | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3618ABG50RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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