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参数资料
| 型号： | R1Q2A3618ABG-50R |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | 36-Mbit QDR™II SRAM 2-word Burst |
| 文件页数： | 10/25页 |
| 文件大小： | 394K |
| 代理商： | R1Q2A3618ABG-50R |
R1Q2A3636/R1Q2A3618/R1Q2A3609
Bus Cycle State Diagram
Read Port NOP
R
Init
= 0
Read Double
Load New
Read Address
Power Up
/R = H
Write Port NOP
/W = H
Supply voltage
provided
Supply voltage
provided
/R = L
Always
/R = L
/R = H
Write Double
at /K
↑
Load New
Write Address
at /K
↑
/W = L
Always
/W = L
/W = H
Notes: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order
is always fixed as: xxx…xxx+0, xxx…xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.
REJ03C0294-0003 Rev.0.03 Jul. 31, 2007
Page 10 of 23
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PDF描述 |
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| R1Q2A3618ABG-60R | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3636 | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3636ABG-40R | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3636ABG-50R | 36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3636ABG-60R | 36-Mbit QDR™II SRAM 2-word Burst |
相关代理商/技术参数 |
参数描述 |
|---|---|
| R1Q2A3618ABG50RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3618ABG50RS0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3618ABG50RT0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3618ABG-60R | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR™II SRAM 2-word Burst |
| R1Q2A3618ABG60RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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