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参数资料
| 型号： | R1Q3A3609ABG-40R |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | 36-Mbit QDR™II SRAM 4-word Burst |
| 文件页数： | 15/26页 |
| 文件大小： | 407K |
| 代理商： | R1Q3A3609ABG-40R |
R1Q3A3636/R1Q3A3618/R1Q3A3609
-30
-33
-40
-50
-60
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Address
valid to K
rising edge
Control
inputs valid
to K rising
edge
Data-in
valid to K,
/K rising
edge
K rising
edge to
address
hold
K rising
edge to
control
inputs hold
K, /K rising
edge to
data-in
hold
Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold
times for all latching clock edges.
2. V
DD
slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V
DD
and input clock are stable. It is recommended that the device is kept inactive during these cycles.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a ±0.1 ns variation from echo
clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured ±100 mV from steady-state voltage.
6. At any given voltage and temperature t
CHQZ
is less than t
CHQX1
and t
CHQZ
less than t
CHQV
.
7. These parameters are sampled.
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.
2. Control input signals may not be operated with pulse widths less than t
KHKL
(min).
3. If C, /C are tied high, K, /K become the references for C, /C timing parameters.
4. V
DDQ
is +1.5 V DC.
5. Control signals are /R, /W, /BW, /BW0, /BW1, /BW2 and /BW3.
BWn signals must operate at the same timing as Data in.
t
AVKH
0.40
0.40
0.50
0.60
0.70
ns
1
t
IVKH
0.40
0.40
0.50
0.60
0.70
ns
1
t
DVKH
0.28
0.30
0.35
0.40
0.50
ns
1
t
KHAX
0.40
0.40
0.50
0.60
0.70
ns
1
t
KHIX
0.40
0.40
0.50
0.60
0.70
ns
1
t
KHDX
0.28
0.30
0.35
0.40
0.50
ns
1
REJ03C0295-0003 Rev.0.03 Jul. 31, 2007
Page 15 of 24
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| R1Q3A3618 | 36-Mbit QDR™II SRAM 4-word Burst |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| R1Q3A3609ABG40RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q3A3609ABG40RS0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q3A3609ABG40RT0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q3A3609ABG-50R | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR™II SRAM 4-word Burst |
| R1Q3A3609ABG50RB0 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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