
Section 14 I2C Bus Interface (IIC)
Rev. 1.00 Mar. 02, 2006 Page 421 of 798
REJ09B0255-0100
Bit
Bit Name
Initial
Value
R/W
Description
1
IRIC
0
R/(W)* I
2C Bus Interface Interrupt Request Flag
Indicates that the I
2C bus interface has issued an
interrupt request to the CPU.
IRIC is set at different times depending on the FS bit in
SAR, the FSX bit in SARX, and the WAIT bit in ICMR.
See section 14.4.7, IRIC Setting Timing and SCL
Control. The conditions under which IRIC is set also
differ depending on the setting of the ACKE bit in
ICCR.
[Setting conditions]
I
2C bus format master mode:
When a start condition is detected in the bus line
state after a start condition is issued.
(When the ICDRE flag, indicating whether or not
transmit data in the first frame is writable, is set to
1.)
When a wait is inserted between the data and
acknowledge bit when the WAIT bit is 1 (fall of the
8th transmit/receive clock)
At the end of data transmission (rise of the 9th
transmit/receive clock while no wait is inserted)
When a slave address is received after bus
arbitration is lost. (When the AAS or AASX flag is
set to 1 after the reception of the first frame
subsequent to the start condition.)
If 1 is received as the acknowledge bit (when the
ACKB bit in ICSR is set to 1 at the completion of
data transmission), when the ACKE bit is 1.
When the AL flag is set to 1 after bus arbitration is
lost while the ALIE bit is 1
I
2C bus format slave mode:
When the slave address (SVA or SVAX) matches
(when the AAS or AASX flag in ICSR is set to 1
after the reception of the first frame subsequent to
the start condition), and at the end of data
transmission up to the subsequent retransmission
start condition or stop condition detection (rise of
the 9th transmit/receive clock)