
Section 14 I2C Bus Interface (IIC)
Rev. 1.00 Mar. 02, 2006 Page 476 of 798
REJ09B0255-0100
A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
B. Set the MST bit to 1.
C. To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Note:
This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
16. Note on Wait Operation in Master Mode
When the interrupt request flag (IRIC) is cleared from 1 to 0 between the falling edge of the
7th clock and the falling edge of the 8th clock in master mode using the wait function, a wait
may not be inserted after the falling edge of the 8th clock and 9th clock pulse may be output
continuously.
When using the wait operation, note the following to clear the IRIC flag.
After the IRIC flag is set to 1 at the rising edge of the 9th clock, clear the IRIC flag before the
rising edge of the 7th clock (when the value of the BC2 to BC0 counter is 2 or more).
If the clearing of the IRIC flag is delayed due to interrupt handling etc. and the value of the BC
counter reaches 1 or 0, confirm that the SCL pin is low and then clear the IRIC flag after the
BC2 to BC0 counter reaches 0 (see figure 14.36).
SCL
12
3
4
5
6
78
9
76
5
76
5
43
2
1
0
12
3
9
A
Transferred data
A
SDA
IRIC
(Sample operation)
IRIC flag can be cleared
IRIC flag can not be cleared
IRIC flag can be cleared
IRIC clear when
BC2 to BC0
≥ 2
IRIC clear
Confirm SCL = L
BC2 to BC0
Figure 14.36 IRIC Flag Clearing Timing in Wait Operation
Note:
This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.