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参数资料
| 型号： | R5109N271A-TR-FE |
| 厂商： | RICOH COMPANY LTD |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封装： | HALOGEN FREE AND ROHS COMPLIANT, SSOP-8 |
| 文件页数： | 13/40页 |
| 文件大小： | 517K |
| 代理商： | R5109N271A-TR-FE |
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R510xx
20
OPERATION
(1) When the power supply, VDD pin voltage becomes more than the released voltage (+VDET), after the released
delay time (or the power on reset time tPLH), the output of RESETB becomes "H" level.
(2) When the SCK pulse is input, the watchdog timer is cleared, and CTW pin mode changes from the discharge
mode to the charge mode. When the CTW pin voltage becomes higher than Vref2H, the mode will change into
the discharge mode, and next watchdog time count starts.
(3) Unless the SCK pulse is input, WDT will not be cleared, and during the charging period of CTW pin,
RESETB
="L".
(4) When the VDD pin becomes lower than the detector threshold voltage (-VDET), RESETB outputs "L" after the
tPHL.
(5) If "L" signal is input to the INH pin, the RESETB outputs "H", regardless the SCK clock state.
(6) During the "L" period of INH pin, the voltage detector monitors the supply voltage.
(7) When the signal to the INH pin is set from "L" to "H", the watchdog starts supervising the system clock, or
charge cycle to the CTW pin starts, the capacitor connected to the CTW pin is charged with the current of
setting Reset time of WDT.
(8) If "L" signal is input to the MR pin, the RESETB outputs "L" after the tMR, regardless the SCK clock state and
VDD voltage.
(9) When the signal to the MR pin is set from "L" to "H", the RESETB outputs "H" after the tPLH, the watchdog
starts supervising the system clock.
Watchdog Timeout period/Reset hold time
The watchdog timeout period and reset hold time can be set with an external capacitor to CTW pin.
The next equations describe the relation between the watchdog timeout period and the external capacitor
value, or the reset hold time and the external capacitor value.
tWD (s)
= 3.1 × 106 × C (F)
tWR (s)
= tWD/9
The watchdog timer (WDT) timeout period is determined with the discharge time of the external capacitor.
During the watchdog timeout period, if the clock pulse from the system is detected, WDT is cleared and the
capacitor is charged. When the charge of the capacitor completes, another watchdog timeout period starts
again. During the watchdog timeout period, if the clock pulse from the system is not detected, during the next
reset hold time RESETB pin outputs "L".
During the reset time, (while charging the external capacitor) and after starting the watchdog timeout period,
(just after from the discharge of the external capacitor) even if the clock pulse is input during the time period
"tWDI", the clock pulse is ignored.
tWDI (s)
= tWD/10
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