参数资料
型号: R5F21142DDD
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, MICROCONTROLLER, PDIP20
封装: 0.300 INCH, 1.78 MM PITCH, PLASTIC, SDIP-20
文件页数: 5/36页
文件大小: 650K
代理商: R5F21142DDD
Rev.0.10
Sep 06, 2004
Page 13 of 34
REJ03B0102-0010Z
Under development
R8C/14, R8C/15 Group
2. Central Processing Unit (CPU)
Preliminary specification
Specifications in this manual are tentative and subject to change.
2.8.7
Interrupt Enable Flag (I Flag)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to “0”, and are enabled when the I flag is set to “1”. The
I flag is set to “0” when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is set to “0”, USP is selected when the U flag is set to “1”.
The U flag is set to “0” when a hardware interrupt request is acknowledged or the INT instruction of
software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has greater priority than IPL, the interrupt is enabled.
2.8.10
Reserved Area
When write to this bit, set to “0”. When read, its content is indeterminate.
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