参数资料
型号: R5F21284KSP
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20
封装: 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20
文件页数: 11/66页
文件大小: 599K
代理商: R5F21284KSP
19
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 1,280/2,304/4,352 data memory locations address both the Register File, the I/O memory, Extended I/O
memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the
standard I/O memory, then 160 locations of Extended I/O memory, and the next 1024/2,048/4,096 locations
address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indi-
rect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the
indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-
register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the
1,024/2,048/4,096 bytes of internal data SRAM in the are all accessible through all these addressing modes. The
Figure 8-2.
Data memory.
8.2.1
Data memory access times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
CPU cycles as described in Figure 8-3 on page 20.
32 Registers
64 I/O Registers
Internal SRAM
(1024 X 8)
(2048 x 8)
(4096 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x04FF/0x08FF/0x10FF
0x0060 - 0x00FF
Data Memory
X 8
160 Ext I/O Reg.
0x0100
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