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参数资料
| 型号： | R5F21284KSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 4.40 X 6.50 MM, 0.65 MM PITCH, PLASTIC, LSSOP-20 |
| 文件页数： | 3/66页 |
| 文件大小： | 599K |
| 代理商： | R5F21284KSP |
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11
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
ands are output from the Register File, the operation is executed, and the result is stored back in the Register File
– in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y- and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes
into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total
SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before sub-
routines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data
SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Reg-
ister
File,
0x2 0
-
0 x 5F.
In
ad dition ,
th e
Atm e l
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P has Extended I/O space from 0x60 -
0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
7.3
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-
functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
7.4
AVR status register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| R5F21284KSP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 16KB Flash 3.3V/5V 20-Pin LSSOP 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 16KB FLASH 3.3V/5V 20PIN LSSOP - Rail/Tube 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 16KB FLASH 20SSOP |
| R5F21284KSP#V0 | 功能描述:IC R8C/28 MCU FLASH 20SSOP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/28 标准包装:60 系列:PSOC® 3 CY8C38xx 核心处理器:8051 芯体尺寸:8-位 速度:67MHz 连通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外围设备:电容感应，DMA，LCD，POR，PWM，WDT 输入/输出数:25 程序存储器容量:64KB（64K x 8） 程序存储器类型:闪存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 电压 - 电源 (Vcc/Vdd):1.71 V ~ 5.5 V 数据转换器:A/D 2x20b，D/A 4x8b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:48-VFQFN 裸露焊盘 包装:托盘 |
| R5F21284KXXXSP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES |
| R5F21284SDSP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MCU |
| R5F21284SDSP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 16KB Flash 3.3V/5V 20-Pin LSSOP 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 16KB FLASH 3.3V/5V 20PIN LSSOP - Rail/Tube 制造商:Renesas Electronics Corporation 功能描述:8BITS FLASH MCU R8C/28 制造商:Renesas Electronics 功能描述:R8C 20MHz 制造商:Renesas Electronics Corporation 功能描述:IC R8C/28 MCU FLASH 20SSOP 制造商:Renesas Electronics Corporation 功能描述:R8C Series 16-bit 1 kB RAM 16 kB Flash 20 MHz Microcontroller - SSOP-20 制造商:Renesas 功能描述:MCU 16-Bit R8C CISC 16KB Flash 3.3V/5V 20-Pin LSSOP |
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