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R8C/3JM Group
7. I/O Ports
R01UH0285EJ0100 Rev.1.00
Aug 08, 2011
7.4.15
I/O Function Pin Select Register (PINSR)
Note:
1. Do not set both the IICTCTWI and IICTCHALF bits to 1 when the I2C bus function is used. Set these bits to 0
when the SSU function is used.
XCSEL Bit (XCIN/XCOUT pin connect bit)
The XCSEL bit is used to connect XCIN and XCOUT to P4_3 and P4_4, respectively. When this bit is set to 1,
XCIN is connected to P4_3 and XCOUT is connected to P4_4. For how to set XCIN and XCOUT, refer to 9.
Clock Generation Circuit.
IOINSEL Bit (I/O port input function select bit)
The IOINSEL bit is used to select the pin level of an I/O port when the PDi_j (j = 0 to 7) bit in the PDi (i = 0 to
4, 6) register is set to 1 (output mode). When this bit is set to 1, the I/O port input function reads the pin input
level regardless of the PDi register.
Table 7.4 lists I/O Port Values Read by Using IOINSEL Bit. The IOINSEL bit can be used to change the input
function of all I/O ports except P4_2.
Address 018Fh
Bit
b7
b6
b5
b4
b3b2b1
b0
Symbol SDADLY1 SDADLY0 IICTCHALF IICTCTWI IOINSEL
—
XCSEL
After Reset
0
0000
0
Bit
Symbol
Bit Name
Function
R/W
b0
XCSEL
XCIN/XCOUT pin connect bit
0: XCIN not connected to P4_3, XCOUT not
connected to P4_4
1: XCIN connected to P4_3, XCOUT connected to
P4_4
R/W
b1
—
Reserved bit
Set to 0.
R/W
b2
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b3
IOINSEL
I/O port input function select bit
0: The I/O port input function depends on the PDi (i =
0 to 4, 6) register.
When the PDi_j (j = 0 to 7) bit in the PDi register is
set to 0 (input mode), the pin input level is read.
When the PDi_j bit in the PDi register is set to 1
(output mode), the port latch is read.
1: The I/O port input function reads the pin input level
regardless of the PDi register.
R/W
b4
IICTCTWI I2C double transfer rate select bit
(1)
0: Transfer rate is the same as the value set with bits
CKS0 to CKS3 in the ICCR1 register
1: Transfer rate is twice the value set with bits CKS0
to CKS3 in the ICCR1 register
R/W
b5
IICTCHALF I2C half transfer rate select bit (1) 0: Transfer rate is the same as the value set with bits
CKS0 to CKS3 in the ICCR1 register
1: Transfer rate is half the value set with bits CKS0 to
CKS3 in the ICCR1 register
R/W
b6
SDADLY0 SDA digital delay select bit
b7 b6
0 0: Digital delay of 3
× f1 cycles
0 1: Digital delay of 11
× f1 cycles
1 0: Digital delay of 19
× f1 cycles
1 1: Do not set.
R/W
b7
SDADLY1
R/W
Table 7.4
I/O Port Values Read by Using IOINSEL Bit
PDi_j bit in PDi register
0 (input mode)
1 (output mode)
IOINSEL bit
0
1
0
1
I/O port values read
Pin input level
Port latch value
Pin input level