
R8C/3JM Group
19. Timer RC
R01UH0285EJ0100 Rev.1.00
Aug 08, 2011
19.6.1
Timer RC Control Register 1 (TRCCR1) in PWM Mode
Notes:
1. Set to these bits when the TSTART bit in the TRCMR register is set to 0 (count stops).
2. If the pin function is set for waveform output (refer to 7.5 Port Settings), the initial output level is output when the
TRCCR1 register is set.
3. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
19.6.2
Timer RC Control Register 2 (TRCCR2) in PWM Mode
Notes:
1. Enabled when in PWM mode.
2. Enabled when in output compare function, PWM mode, or PWM2 mode. For notes on PWM2 mode, refer to
3. Enabled when in PWM2 mode.
Address 0121h
Bit
b7b6b5
b4b3b2
b1b0
Symbol
After Reset
000
00
Bit
Symbol
Bit Name
Function
R/W
b0
TOA
TRCIOA output level select bit
(1)Disabled in PWM mode
R/W
b1
TOB
TRCIOB output level select bit
(1, 2)0: Initial output selected as non-active level
1: Initial output selected as active level
R/W
b2
TOC
TRCIOC output level select bit
(1,
2)R/W
b3
TOD
TRCIOD output level select bit
(1,
2)R/W
b4
TCK0
Count source select bit
(1)b6 b5 b4
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRCCLK input rising edge
1 1 0: fOCO40M
R/W
b5
TCK1
R/W
b6
TCK2
R/W
b7
CCLR
TRC counter clear select bit
0: Disable clear (free-running operation)
1: Clear by compare match in the TRCGRA register
R/W
Address 0130h
Bit
b7b6b5
b4b3b2
b1b0
Symbol
After Reset
000
110
00
Bit
Symbol
Bit Name
Function
R/W
b0
POLB
PWM mode output level control
0: TRCIOB output level selected as “L” active
1: TRCIOB output level selected as “H” active
R/W
b1
POLC
PWM mode output level control
0: TRCIOC output level selected as “L” active
1: TRCIOC output level selected as “H” active
R/W
b2
POLD
PWM mode output level control
0: TRCIOD output level selected as “L” active
1: TRCIOD output level selected as “H” active
R/W
b3
—
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
—
b4
—
b5
CSEL
TRC count operation select bit
(2)0: Count continues at compare match with the
TRCGRA register
1: Count stops at compare match with the TRCGRA
register
R/W
b6
TCEG0 TRCTRG input edge select bit
(3)b7 b6
0 0: Disable the trigger input from the TRCTRG pin
0 1: Rising edge selected
1 0: Falling edge selected
1 1: Both edges selected
R/W
b7
TCEG1
R/W