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R01DS0033EJ0200 Rev.2.00
Page 11 of 115
Feb 07, 2011
M16C/63 Group
1. Overview
Figure 1.7
Pin Assignment for the 100-Pin Package
26
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2
3
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63
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100
99
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80
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M16C/63 Group
PLQP0100KB-A
(100P6Q-A)
(Top view)
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/CTS6/RTS6/D8
P1_1/CLK6/D9
P1_2/RXD6/SCL6/D10
VREF
AVSS
AVCC
P10_0/AN0/KI4
P10_1/AN1/KI5
P10_2/AN2/KI6
P10_3/AN3/KI7
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_7/ADTRG/SIN4
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P1_
3
/TXD
6
/SD
A6/
D
11
P1_
4
/D
12
P3_
1
/A
9
P3_
2
/A
10
P3_
3
/A
11
P3_
4
/A
12
P3_
5
/A
13
P3_
6
/A
14
P3_
7
/A
15
P4_
0
/A
16
P4_
1
/A
17
V
CC2
VSS
P4_2/A18
P4_3/A19
P5_6/ALE
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
P5_7/RDY/CLKOUT
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P6_0/TRHO/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P5_0/WRL/WR
P5_1/WRH/BHE
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
V
CC1
XI
N
XO
UT
VS
S
R
ESET
CN
VS
S
P8
_
7
/XC
IN
P8
_6/X
C
O
U
T
BYTE
P7
_4
/T
A
2O
U
T
/W
P
9_3
/DA0
/T
B
3
IN/
P
W
M
0
P
9_4
/DA1
/T
B
4
IN/
P
W
M
1
P9
_1
/T
B
1
IN/
P
MC
1/
SIN3
P9
_2
/T
B
2
IN/
P
MC
0/
SO
U
T
3
P8
_2
/I
N
T
0
P8
_3
/I
N
T
1
P8
_5
/N
M
I/S
D
/CE
C
(1)
P
9_0/
TB0
IN/C
L
K3
P8
_4
/I
NT
2/
Z
P
7
_
5
/TA2
IN/W
P7_
3
/C
TS2/R
T
S2/
T
A1
IN
/V
P
7
_
6
/TA
3
OUT/TX
D
5
/S
DA5
P
7_7/
TA3
IN/C
L
K5
P8
_0/TA
4OU
T
/U
/R
XD
5/S
C
L5
P8
_1
/T
A
4
IN/
U
/CTS
5/RTS5
P4_5/CLK7/CS1
P4_4/CTS7/RTS7/CS0
P3_
0
/A
8
[A8
/D7
]
P2_
0
/A
N
2
_0
/A0
,[A
0/D0],
A0
P2_
1
/A
N
2
_1
/A1
,[A
1/D1],
[A1
/D0]
P2_
2
/A
N
2
_2
/A2
,[A
2/D2],
[A2
/D1]
P2_
3
/A
N
2
_3
/A3
,[A
3/D3],
[A3
/D2]
P2_
4
/I
NT6
/AN
2_
4/A
4
,[
A
4/D
4
],
[A4/
D3
]
P2_
5
/I
NT7
/AN
2_
5/A
5
,[
A
5/D
5
],
[A5/
D4
]
P2_
6
/A
N
2
_6
/A6
,[A
6/D6],
[A6
/D5]
P2_
7
/A
N
2
_7
/A7
,[A
7/D7],
[A7
/D6]
See Note 3
P1_
5
/I
N
T
3
/IDV/D1
3
P1_
6
/I
N
T
4
/IDW
/D1
4
P
1
_7
/I
N
T
5/IDU/D1
5
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
VCC2 ports
VCC1 ports
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal.
They should not be considered as two separate functional signals.