R01DS0033EJ0200 Rev.2.00
Page 10 of 115
Feb 07, 2011
M16C/63 Group
1. Overview
1.5
Pin Assignments
Figure 1.6
Pin Assignment for the 100-Pin Package
56
55
54
53
52
51
1
M16C/63 Group
PRQP0100JD-B
(100P6F-A)
(
Top view)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
VREF
AVSS
VC
C
1
XI
N
XO
UT
VS
S
RE
SE
T
CNV
SS
P
8_7
/XC
IN
P
8_6/XC
OU
T
BY
T
E
P7_4
/T
A2O
U
T/
W
AVCC
P10_0/AN0/KI4
P10_1/AN1/KI5
P10_2/AN2/KI6
P10_3/AN3/KI7
P
9_3/DA
0/T
B
3IN/P
W
M0
P
9_4/DA
1/T
B
4IN/P
W
M1
P9_5/AN
EX0
/C
LK4
P
9_6/A
N
E
X
1
/S
O
U
T
4
P
9_1/T
B1IN/
PM
C
1
/S
IN3
P
9_2/T
B2IN/PM
C0
/S
OU
T
3
P7_2
/C
LK2/TA
1OU
T
/V
P8_2
/I
N
T
0
P7_1/
RX
D
2
/S
CL2/S
C
LMM
/T
A
0
IN/
TB5IN
(1
)
P8_3
/I
N
T
1
P8
_
5
/N
MI
/S
D/
CE
C
(1
)
P9_7/ADTRG/SIN4
P9_0
/TB
0
IN
/C
LK3
P7_0/TX
D2/
S
DA
2/S
D
AM
M/
TA0O
UT
(1
)
P
8
_
4
/I
NT
2/ZP
P7_
3/CTS2/R
TS2/TA
1IN
/V
P7
_5/T
A
2IN/
W
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P5_6/ALE
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
P5_7/RDY/CLKOUT
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P6_0/TRHO/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P5_0/WRL/WR
P5_1/WRH/BHE
P
1_4/D
1
2
P
3_1/A
9
P
3_2/A
1
0
P
3_3/A
1
P
3_4/A
1
2
P
3_5/A
1
3
P
3_6/A
1
4
P
3_7/A
1
5
P
4_0/A
1
6
P
4_1/A
1
7
P
4_2/A
1
8
P
4_3/A
1
9
VC
C
2
VS
S
P
7_6
/TA3O
U
T
/TX
D
5
/S
DA5
P7_7
/TA
3
IN
/C
LK5
P8_0/
TA
4OU
T
/U
/R
XD5
/SCL5
P
8_1/T
A
4IN/U/C
T
S
5
/R
TS5
P
1_0/C
T
S
6
/R
TS6/
D8
P
1_1/C
L
K
6
/D
9
P
1_2/R
X
D6/S
CL
6/D
1
0
P
1_3/T
XD
6
/S
DA6
/D
1
P4_5/CLK7/CS1
P4_4/CTS7/RTS7/CS0
P
3_0/A
8
[
A
8/D7]
P
2_0/A
N
2_0/A
0
,[A
0
/D0],
A0
P
2_1/A
N
2_1/A
1
,[A
1
/D1],
[
A
1/D0]
P
2_2/A
N
2_2/A
2
,[A
2
/D2],
[
A
2/D1]
P
2_3/A
N
2_3/A
3
,[A
3
/D3],
[
A
3/D2]
P
2_4/IN
T6/A
N
2_4/A
4
,[A
4/D4]
,[A
4/D
3
]
P
2_5/IN
T7/A
N
2_5/A
5
,[A
5/D5]
,[A
5/D
4
]
P
2_7/A
N
2_7/A
7
,[A
7
/D7],
[
A
7/D6]
See Note 3
P
2_6/A
N
2_6/A
6
,[A
6
/D6],
[
A
6/D5]
P
1_5/IN
T3/ID
V/D13
P
1_6/IN
T4/ID
W/D14
P
1_7/IN
T5/ID
U/D
15
P4_6/PWM0/RXD7/SCL7/CS2
P4_7/PWM1/TXD7/SDA7/CS3
VCC2 ports
VCC1 ports
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal.
They should not be considered as two separate functional signals.