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参数资料
| 型号： | R5F364AMNFB |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件页数： | 79/90页 |
| 文件大小： | 1261K |
| 代理商： | R5F364AMNFB |
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Page 80 of 88
5. Electrical Characteristics
VCC1 = VCC2 = 3 V
5.3.4
Switching Characteristics (Memory Expansion Mode and Microprocessor
Mode)
(VCC1 = VCC2 = 3 V, VSS = 0 V, at Topr = -20 to 85°C/-40 to 85°C unless otherwise specified)
5.3.4.1
In No Wait State Setting
Notes:
1.
Calculated according to the BCLK frequency as follows:
f
f(BCLK) is 12.5 MHz or less.
2.
Calculated according to the BCLK frequency as follows:
This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
CR × ln(1 V
OL/VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t =
30 pF × 1 kΩ × In(1 0.2V
CC2/VCC2)
= 6.7 ns.
Table 5.54
Memory Expansion and Microprocessor Modes (in No Wait State Setting)
Symbol
Parameter
Measuring
Condition
Standard
Unit
Min.
Max.
td(BCLK-AD)
Address output delay time
See
30
ns
th(BCLK-AD)
Address output hold time (in relation to BCLK)
0ns
th(RD-AD)
Address output hold time (in relation to RD)
0ns
th(WR-AD)
Address output hold time (in relation to WR)
ns
td(BCLK-CS)
Chip select output delay time
30
ns
th(BCLK-CS)
Chip select output hold time (in relation to BCLK)
0ns
td(BCLK-ALE)
ALE signal output delay time
25
ns
th(BCLK-ALE)
ALE signal output hold time
4ns
td(BCLK-RD)
RD signal output delay time
30
ns
th(BCLK-RD)
RD signal output hold time
0ns
td(BCLK-WR)
WR signal output delay time
30
ns
th(BCLK-WR)
WR signal output hold time
0ns
td(BCLK-DB)
Data output delay time (in relation to BCLK)
40
ns
th(BCLK-DB)
Data output hold time (in relation to BCLK) (3)
0ns
td(DB-WR)
Data output delay time (in relation to WR)
ns
th(WR-DB)
Data output hold time (in relation to WR) (3)
ns
td(BCLK-HLDA)
HLDA output delay time
40
ns
0.5
10
9
×
f
BCLK
()
----------------------40 ns
[]
–
0.5
10
9
×
f
BCLK
()
----------------------10 ns
[]
–
DBi
R
C
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相关代理商/技术参数 |
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| R5F364AMNFB#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-bit M16C CISC 528KB Flash 5V 100-Pin LQFP Tray 制造商:Renesas Electronics Corporation 功能描述:M16C64A 512/31KB -20 85C 100LQFP - Trays 制造商:Renesas Electronics 功能描述:Tray 制造商:Renesas 功能描述:MCU 16-bit M16C CISC 528KB Flash 5V 100-Pin LQFP Tray |
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| R5F36506CDFB#V0 | 制造商:Renesas Electronics Corporation 功能描述:M16C/65C 144+8/12 100LQFP 14X14 -40 TO +85 - Trays |
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