参数资料
型号: R5F56218BDBG#U0
厂商: Renesas Electronics America
文件页数: 17/148页
文件大小: 0K
描述: MCU 32BIT FLASH 512KROM 176LFBGA
产品培训模块: RX Compare Match Timer
RX DMAC
标准包装: 1
系列: RX600
核心处理器: RX
芯体尺寸: 32-位
速度: 100MHz
连通性: CAN,EBI/EMI,I²C,SCI,SPI,USB
外围设备: DMA,LVD,POR,PWM,WDT
输入/输出数: 126
程序存储器容量: 512KB(512K x 8)
程序存储器类型: 闪存
RAM 容量: 96K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.6 V
数据转换器: A/D 8x10/12b,D/A 2x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 176-LFBGA
包装: 托盘
2004 Microchip Technology Inc.
DS39609B-page 111
PIC18F6520/8520/6620/8620/6720/8720
10.4
PORTD, TRISD and LATD
Registers
PORTD is an 8-bit wide, bidirectional port. The corre-
sponding data direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled, by setting
the
EBDIS
bit
in
the
MEMCOM
register
(MEMCON<7>). When operating as the external mem-
ory interface, PORTD is the low-order byte of the
multiplexed address/data bus (AD7:AD0).
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.10 “Parallel Slave
Port” for additional information on the Parallel Slave
Port (PSP).
EXAMPLE 10-4:
INITIALIZING PORTD
FIGURE 10-9:
PORTD BLOCK DIAGRAM IN I/O PORT MODE
Note:
On a Power-on Reset, these pins are
configured as digital inputs.
CLRF
PORTD
; Initialize PORTD by
; clearing output
; data latches
CLRF
LATD
; Alternate method
; to clear output
; data latches
MOVLW
0xCF
; Value used to
; initialize data
; direction
MOVWF
TRISD
; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Data Bus
WR LATD
WR TRISD
Data Latch
TRIS Latch
RD TRISD
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LATD
or PORTD
0
1
Q
0
1
P
N
VDD
VSS
0
1
RD PORTD
PSP Read
PSP Write
Note 1:
I/O pins have diode protection to VDD and VSS.
TTL Buffer
Schmitt Trigger
Input Buffer
PORTD/CCP1 Select
PSPMODE
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