R01UH0040EJ0100 Rev.1.00
Page 201 of 1657
Sep 8, 2011
RX630 Group
6. Resets
6.3.4
Deep Software Standby Reset
This is an internal reset generated when deep software standby mode is canceled by an interrupt.
When a deep software standby mode cancelation source is generated, a deep software standby reset is generated. The
deep software standby reset is canceled after tDSBY (return time after deep software standby mode cancelation) has
elapsed. At the same time, deep software standby mode is also canceled.
When tDSBYWT (wait time after deep software standby mode cancelation) has elapsed after deep software standby
mode has been canceled, the internal reset is canceled and the CPU starts the reset exception handling.
6.3.5
Independent Watchdog Timer Reset
Independent watchdog timer reset is an internal reset generated by the independent watchdog timer.
Output of the independent watch dog timer reset from the independent watchdog timer can be selected by settings in the
IWDT reset control register (IWDTRCR) or option function select register 0 (OFS0).
When output of the independent watch dog timer reset is selected, an independent watchdog timer reset is generated if
the independent watchdog timer underflows, or if data is written when refresh operation is disabled. When the internal
reset time (tRESW2) has elapsed after the independent watchdog timer reset has been generated, the internal reset is
canceled and the CPU starts the reset exception handling.
6.3.6
Watchdog Timer Reset
The watchdog-timer reset is an internal reset from the watchdog timer.
Output of the independent watch dog timer reset from the independent watchdog timer can be selected by settings in the
WDT reset control register (WDTRCR) or option function select register 0 (OFS0).
When output of the independent watch dog timer reset is selected, a watchdog timer reset is generated if the watchdog
timer underflows, or if data is written when refresh operation is disabled. When the internal reset time (tRESW2) has
elapsed after the watchdog timer reset is generated, the internal reset is canceled and the CPU starts the reset exception
handling.
6.3.7
Software Reset
The software reset is an internal reset generated by the software reset circuit.
When A501h is written to SWRR, a software reset is generated. When the internal reset time (tRESW2) has elapsed after
the software reset is generated, the internal reset is canceled and the CPU starts the reset exception handling.