R01UH0040EJ0100 Rev.1.00
Page 206 of 1657
Sep 8, 2011
RX630 Group
7. Option-Setting Memory
Note 1. As for the blank product, the IWDTCKS[3:0] and WDTCKS[3:0] bits are 1111b (setting prohibited). The IWDTCKS[3:0] or
WDTCKS[3:0] bits should be changed when the IWDT or WDT is activated in auto start mode by setting the IWDTSTRT or
WDTSTRT bit to 0.
The OFS0 register is allocated in the ROM. Set this register at the same time as writing the program. After writing to the
OFS0 register once, do not write to it again.
When erasing the block including the OFS0 register, the OFS0 register value becomes FFFF FFFFh.
The setting in the OFS0 register is ineffective in user boot mode and USB boot mode, and the value becomes FFFF
FFFFh.
IWDTSTRT Bit (IWDT Start Mode Select)
This bit selects the mode in which the IWDT is activated after a reset (stopped state or activated in auto-start mode).
When activated in auto-start mode, the OFS0 register setting for the IWDT is effective.
IWDTTOPS[1:0] Bits (IWDT Timeout Period Select)
These bits select the timeout period, i.e. the time it takes for the downcounter to underflow, as 1024, 4096, 8192, or
16384 cycles of the frequency-divided clock set by the IWDTCKS[3:0] bits. The time (number of LOCO clock cycles
for IWDT) it takes to underflow after a refresh operation is determined by the combination of the IWDTCKS[3:0] bits
and IWDTTOPS[1:0] bits.
IWDTCKS[3:0] Bits (IWDT Clock Frequency Division Ratio Select)
These bits select, from 1/1, 1/16, 1/32, 1/64, 1/128, and 1/256, the division ratio of the prescaler to divide the frequency
of the LOCO clock for IWDT. Using the setting of these bits together with the IWDTTOPS[1:0] bit setting, the IWDT
counting period can be set from 1024 to 4194304 LOCO clock cycles for IWDT.
b19, b18
WDT Timeout Period Select
b19 b18
0 0: 1024 cycles (03FFh)
0 1: 4096 cycles (0FFFh)
1 0: 8192 cycles (1FFFh)
1 1: 16384 cycles (3FFFh)
R
b23 to b20
WDT Clock Frequency
Division Ratio Select
b23
b20
0 0 0 1: PCLK/4
0 1 0 0: PCLK/64
1 1 1 1: PCLK/128
0 1 1 0: PCLK/512
0 1 1 1: PCLK/2048
1 0 0 0: PCLK/8192
Settings other than above are prohibited.
R
b25, b24
WDT Window End Position
Select
b25 b24
0 0: 75%
0 1: 50%
1 0: 25%
1 1: 0% (No window end position setting)
R
b27, b26
WDT Window Start Position
Select
b27 b26
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100% (No window start position setting)
R
b28
WDT Reset Interrupt Request
Select
0: Non-maskable interrupt request is enabled
1: Reset is enabled
R
b31 to b29
—
Reserved
When reading, this bit returns to the value written by the
user. The write value should be 1.
R
Bit
Symbol
Bit Name
Description
R/W