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参数资料
| 型号： | R5F6460EJFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 30/75页 |
| 文件大小： | 663K |
| 代理商： | R5F6460EJFP |
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55
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
When the BOOTRST Fuse is programmed and the Boot section size set to 4Kbytes, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address
Labels Code
Comments
.org 0x0002
0x0002
jmp
EXT_INT0
; IRQ0 Handler
0x0004
jmp
PCINT0
; PCINT0 Handler
...
;
0x002C
jmp
SPM_RDY
; Store Program Memory Ready Handler
;
.org 0x3800/0x7800
0x3800/0x7801RESET:ldir16,high(RAMEND); Main program start
0x3801/0x7801
out
SPH,r16
; Set Stack Pointer to top of RAM
0x3802/0x7802
ldi
r16,low(RAMEND)
0x3803/0x7803
out
SPL,r16
0x3804/0x7804
sei
; Enable interrupts
0x3805/0x7805
<instr>
xxx
When the BOOTRST Fuse is programmed, the Boot section size set to 4Kbytes and the IVSEL bit in the MCUCR
Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and
Interrupt Vector Addresses is:
Address
Labels Code
Comments
;
.org 0x3800/0x7800
0x3800/0x7800
jmp
RESET
; Reset handler
0x3802/0x7802
jmp
EXT_INT0
; IRQ0 Handler
0x3804/0x7804
jmp
PCINT0
; PCINT0 Handler
...
;
0x382C/0x782C
jmp
SPM_RDY
; Store Program Memory Ready Handler
;
0x382E/0x782ERESET:ldir16,high(RAMEND); Main program start
0x382F/0x782F
out
SPH,r16
; Set Stack Pointer to top of RAM
0x3830/0x7830
ldi
r16,low(RAMEND)
0x3831/0x7831
out
SPL,r16
0x3832/0x7832
sei
; Enable interrupts
0x3833/0x7833
<instr>
xxx
12.2
Moving interrupts between application and Boot Space
The General Interrupt Control Register controls the placement of the Interrupt Vector table, see ”MCUCR – MCU
To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the
IVSEL bit:
a.
Write the Interrupt Vector Change Enable (IVCE) bit to one.
b.
Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE
is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, inter-
rupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Note:
If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed, interrupts are dis-
abled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot
Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the sec-
tion ”Boot Loader Support – Read-While-Write Self-Programming” on page 241 for details on Boot Lock bits.
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