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参数资料
| 型号： | R5F6460EJFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 67/75页 |
| 文件大小： | 663K |
| 代理商： | R5F6460EJFP |
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89
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
Figure 15-5. CTC Mode, timing diagram.
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP
to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with
care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will
not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have
a maximum frequency of f
OC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by
the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts
from MAX to 0x00.
15.7.3
Fast PWM mode
The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter
counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting
Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope oper-
ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that
use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectifi-
cation, and DAC applications. High frequency allows physically small sized external components (coils,
capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then
cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 15-6 on
page 90. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation.
The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0
slopes represent compare matches between OCR0A and TCNT0.
TCNTn
OCn
(Toggle)
OCnx Interrupt Flag Set
1
4
Period
2
3
(COMnx1:0 = 1)
f
OCnx
fclk_I/O
2 N
1
OCRnx
+
--------------------------------------------------
=
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