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参数资料
| 型号： | R75603BSA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 锁存器 |
| 英文描述： | AC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDFP20 |
| 封装： | CERAMIC, DFP-20 |
| 文件页数： | 2/10页 |
| 文件大小： | 224K |
| 代理商： | R75603BSA |
National P/N 54AC377 - Octal D Flip-Flop with Clock Enable
Full
production
N/A
50+ $13.6000
rail
of
19
[logo]ZS4A$E
JM38510/
75603BSA
27014 QS
R75603BSA
Full
production
N/A
50+ $73.0000
rail
of
19
[logo]ZS4A$E
JM38510R
75603BSA
27014 QS
JM54AC377S2A-
RH
20 MSL
Full
production
N/A
rail
of
N/A
[logo]ZS4A
27014 Q$E
JM38510R
75603S2A
JM54AC377SRA-
RH
20 MSL
Full
production
N/A
rail
of
N/A
[logo]ZS4A$E
JM38510R75603SRA
27014 Q
RM54AC377SSA
N/A
rail
of
N/A
[logo]ZS4A$E
RM54AC377
SSA WAFER #
R
Full
production
N/A
50+ $138.0000
rail
of
19
[logo]ZS4A$E
27014 JM38510/
75603SSA Q
Full
production
N/A
50+ $138.0000
rail
of
19
[logo]ZS4A$E
27014 JM38510R
75603SSA Q
General Description
The 'AC/'ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The
common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE#) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop's Q output. The CE# input must be stable only one
setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Features
q
ICC reduced by 50%
q
Ideal for addressable register applications
q
Clock enable for address and data synchronization applications
q
Eight edge-triggered D flip-flops
q
Buffered common clock
q
Outputs source/sink 24 mA
q
See '273 for master reset version
q
See '373 for transparent latch version
q
See '374 for TRI-STATE version
q
'ACT377 has TTL-compatible inputs
q
Standard Microcircuit Drawing (SMD) -'AC377: 5962-88702 -'ACT377: 5962-87697
[Information as of 5-Aug-2002]
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