参数资料
型号: R8820LV
厂商: Electronic Theatre Controls, Inc.
英文描述: 16-BIT RISC MICROCONTROLLER
中文描述: 16位RISC微控制器
文件页数: 12/98页
文件大小: 1000K
代理商: R8820LV
R DC
RISC DSP Controller
R8820LV
RDC Semiconductor Co.
Rev:1.0
Subject to change without notice
12
65
66
2
PCS /
1
STS /
PCS /PIO17
0
PCS /PIO16
ENRX /PIO18
peripheral memory block (I/O or memory address). For I/O
accessed, the base address can be programmed in the region
00000h to 0FFFFh.
For memory address access, the base address can be located in
the 1M byte memory address region. These pins assert with the
multiplexed AD address bus and are not float during bus hold.
Interrupt Control Unit Interface
Nonmaskable Interrupt. The NMI is the highest priority
hardware interrupt and is nonmaskable. When this pin is
asserted (NMI transition from low to high), the microcontroller
always transfers the address bus to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt
vector table. The NMI pin must be asserted for at least one
CLKOUTA period to guarantee that the interrupt is recognized.
Maskable interrupt request 4. Act high. This pin indicates that
an interrupt request has occurred. The microcontroller will
jump to the INT4 address vector to execute the service routine
if the INT4 is enable. The interrupt input can be configured to
be either edge- or level-triggered. The requesting device must
holt the INT4 until the request is acknowledged to guarantee
interrupt recognition.
Maskable interrupt request 3/interrupt acknowledge 1/slave
interrupt request. For INT3 feature, except the difference
interrupt line and interrupt address vector, the function of INT3
is the same as INT4.
For
1
INTA feature, in cascade mode or special fully-nested
mode, this pin corresponds the INT1.
For IRQ feature, when the microcontroller is as a slave device,
this pin issues an interrupt request to the master interrupt
controller.
Maskable interrupt request 2/interrupt acknowledge 0. For
INT2 feature, except the difference interrupt line and interrupt
address vector, the function of INT2 is the same as INT4.
For
0
INTA feature, in cascade mode or special fully-nested
mode, this pin corresponds the INT0.
Maskable interrupt request 1/slave select. For INT1 feature,
except the difference interrupt line and interrupt address vector,
the function of INT1 is the same as INT4.
For SELECTfeature, when the microcontroller is as a slave
device, this pin is drived from the master interrupt controller
decoding. This pin acts to indicate that an interrupt appears on
the address and data bus.
The INT0 must act before SELECTacts when the interrupt
type appears on the bus.
Maskable interrupt request 0. Except the interrupt line and
interrupt address vector, the function of INT0 is the same as
INT4.
Timer Control Unit Interface
Timer input. These pins can be as clock or control signal input,
which depend upon the programmed timer mode. After
internally synchronizing low to high transitions on TMRIN, the
timer controller increments. These pins must be pull-up if not
being used.
Output/Inputprovide single pulse or continuous waveform. The duty cycle
47
NMI
Input
52
INT4/PIO30
Input/Output
53
INT3/
1
INTA /IRQ
Input/Output
54
INT2/
0
INTA /PIO31
Input/Output
55
INT1/SELECT
Input/Output
56
INT0 / SO1
Input/Output
72
75
TMRIN1/PIO0
TMRIN0/PIO11
Input/Output
73
74
TMROUT1/PIO1
TMROUT0/PIO10
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