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参数资料
型号： RCPXA271FC0416
厂商： MARVELL SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 416 MHz, MICROPROCESSOR, PBGA336
封装： 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数： 105/138页
文件大小： 1048K
代理商： RCPXA271FC0416
Part 2: Flash Device Operations
Flash Read Operations
Intel PXA27x Processor Family Memory Subsystem
69
Flash Read Operations
10
The flash supports two read modes: asynchronous page-mode and synchronous burst-mode.
Asynchronous page-mode is the default read mode after flash power-up or a reset. The Read
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see Section 10.3, “Flash Read Configuration Register” on page 70).
To perform a read operation, F-RST# and WE# must be deasserted while F-CE# and OE# are
asserted. F-CE# is the flash-select control. When asserted, it enables the flash memory. OE# is the
data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus.
See Section 10.3, “Flash Read Configuration Register” on page 70 for details on the available read
modes, and Section 15, “Special Flash Read States” on page 93 for details regarding the available
read states.
The Automatic Power Savings (APS) feature provides low power operation following reads during
active mode. After data is read from the memory array and the address lines are quiescent, APS
automatically places the flash into standby. In APS, flash current is reduced to ICCAPS (see
Section 6.1, “Flash DC Current Characteristics” on page 37).
Each partition of the flash can be in any of four read states: Read Array, Read Identifier, Read
Status or Read Query. Upon power-up, or after a reset, all partitions of the flash default to Read
Array. To change a partition’s read state, the appropriate read command must be written to the flash
(see Section 9.3, “Flash Command Definitions” on page 66).
10.1
Flash Asynchronous Page-Mode Read
Following a flash power-up or reset, asynchronous page-mode is the default flash read mode and
all partitions are set to Read Array. However, to perform array reads after any other flash operation
(e.g. write operation), the Read Array command must be issued in order to read from the flash
memory array.
Note:
Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR.15 is set (see Section 10.3, “Flash Read Configuration Register” on page 70).
To perform an asynchronous page-mode read, an address is driven onto A[MAX:MIN], and F-CE#
and ADV# are asserted. WE# and F-RST# must already have been deasserted. ADV# can be
driven high to latch the address, or it must be held low throughout the read cycle. F-CLK is not
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads are to be
performed, F-CLK should be tied to a valid VIH level, and ADV# must be tied to ground. Flash
array data are driven onto DQ[15:0] after an initial access time tAVQV delay. (see Section 7.2,
“Flash AC Read Specifications” on page 42).
In asynchronous page-mode, four-data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on A[MAX:MIN] is driven onto DQ[15:0] after the initial access delay. Address bits
A[MAX:MIN+2] select the 4-word page. Address bits A[MIN+1:MIN] determine which word of
the 4-word page is output from the data buffer at any given time.
Note:
AMIN for a 16-bit operations is A1 while a 32-bit operations, AMIN = A2 on the package ballout.
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