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参数资料
型号： RCPXA271FC0416
厂商： MARVELL SEMICONDUCTOR INC
元件分类： 微控制器/微处理器
英文描述： 416 MHz, MICROPROCESSOR, PBGA336
封装： 14 X 14 MM, 1.55 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, CSP-336
文件页数： 5/138页
文件大小： 1048K
代理商： RCPXA271FC0416
Part 3: LPSDRAM Operations
LPSDRAM Command and Operation
102
Intel PXA27x Processor Family Memory Subsystems
A read burst can be terminated by a subsequent write command, and data from a fixed length read
burst can be followed by a write command. The write command may be initiated on the clock edge
immediately following the last data element from the read burst, provided the I/O contention could
be avoided. D-DM[1:0] can be used to control I/O contention as shown in Figure 38, “LPSDRAM
Read to LPSDRAM Write Command” on page 106. D-DM[1:0] latency is 2 clocks for output
buffers masking, so the D-DM[1:0] signal must be set high at least 2 clocks prior to the write
command. D-DM[1:0] latency for Write is zero clocks, so D-DM[1:0] must be set low before write
command to ensure data written is not masked.
A read burst may be followed by or truncated with a Precharge command, which could be issued
CL-1 cycles before the last desired element. This is shown in Figure 39, “LPSDRAM Read
Command Followed by Precharge” on page 106. Following Precharge command, another
command to the same bank cannot be issued until tRP is met. Similarly Burst Terminate command
can be used to stop a burst as shown in Figure 40, “LPSDRAM Read Followed by Burst
Terminate” on page 106.
17.4
LPSDRAM Write Command
The write command is used to initiate a burst write access to an active row. The value of D-BA[1:0]
select the bank and address inputs select the starting column location. The value of A11 determines
whether or not auto precharge is used. Input data appearing on the data bus, is written to the
memory array subject to the D-DM[1:0] input logic level appearing coincident with the data.
D-DM[1:0] latency for write command is 0-clock cycle.
The burst length is set in the mode register. The starting column and bank address is provided along
with the auto precharge option. The first valid data-in is registered coincident with the Write
command. Subsequent data elements will be registered on each successive positive clock edge.
Figure 39, “LPSDRAM Read Command Followed by Precharge” on page 106 shows 2
consecutive 4 word write bursts. A write burst may be followed by or truncated with a Precharge
command to the same bank. The Precharge should be issued tWR after the clock edge after the last
desired input data is entered. In addition, when truncating a Write burst, the D-DM[1:0] signal
must be used to mask input data for the clock edge coincident with the precharge command. This is
shown in Figure 42 and Figure 43 on page 107, where tWR corresponds to either 1 or 2 clock
cycles, respectively. Following the Precharge command, a subsequent command cannot be issued
to the same bank until tRP is met.
Write Burst can be truncated with a Burst Terminate command. While truncating, the input data
being applied coincident to the Burst Terminate will be ignored.
Data for any Writes may be truncated by a subsequent Read command as shown in Figure 44 on
page 108. Once the Read command is registered, the Data inputs will be ignored.
17.5
LPSDRAM Power-Down
Power down occurs if D-CKE is set low coincident with LPSDRAM Deselect or NOP command
and when no accesses are in progress. If power down occurs when all banks are idle, it is Precharge
Power-Down. If power down occurs when one or more banks are active, it is referred to as Active
power down. The LPSDRAM cannot stay in this mode for longer than the refresh period (64 ms)
without losing data. The power down state is exited by setting D-CKE high while issuing a
LPSDRAM Deselect or NOP command. This is shown in Figure 45 on page 108.
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