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参数资料
| 型号： | RD151TS3326ARPH0 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 80 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 3.95 X 4.90 MM, 1.27 MM PITCH, PLASTIC, SOP-8 |
| 文件页数： | 8/11页 |
| 文件大小： | 103K |
| 代理商： | RD151TS3326ARPH0 |
RD151TS3316ARP, RD151TS3326ARP
Rev.1.00 May 11, 2006 page 4 of 8
AC Electrical Characteristics / SSC Clock Output
Ta = 25°C, VDD = 3.3 V, CL = 15 pF
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Notes
Operating current
IDD
—
18
24
mA
VDD = 3.3 V, CL = 15 pF,
XIN = 40 MHz
Cycle to cycle jitter *
1
tCCS
—
|100|
—
ps
SEL = 0, CL = 0 pF
SSC=
±1.5%(TS3316ARP)
SSC= -3.0%(TS3326ARP)
Figure 1
Slew rate
tSL
—
0.7
4.0
V/ns
VDD = 3.3 V,
0.2
× VDD to 0.8 × VDD
Clock duty cycle
45
50
55
%
Stabilization time
*2
—
2
ms
Notes: Parameters are target of design. Not 100% tested in production.
1. Cycle to cycle jitter is included spread spectrum modulation.
2. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input signal after
power up.
SSCOUT
tcycle n
tCCS = (tcycle n) – (tcycle n+1)
tcycle n+1
Figure 1 Cycle to cycle jitter
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