参数资料
型号: RD151TS501US
厂商: Renesas Technology Corp.
英文描述: PLL clock generator series
中文描述: PLL时钟发生器系列
文件页数: 2/7页
文件大小: 104K
代理商: RD151TS501US
RD151TS501US
REJ03D0897-0102 Rev.1.02 Apr 25, 2007
Page 2 of 6
Block Diagram
1/M
1/N
VDD
VSS
IN
OUT
PDWN
Synthesizer
DIV
SEL
DIV2
Rpd = 100 k
Rpd = 100 k
Rpd = 100 k
Rpd = 100 k
Pin Descriptions
Pin name
VDD
VSS
OUT
PDWN
SEL
IN
DIV2
No.
1,2
3
4
5
6
7
8
Type
Power
Ground
Output
Input
Input
Input
Input
Description
Power supply
GND
Clock signal output
Power-down control *
1
Frequency select *
1
Clock signal input *
1
Frequency select *
1
Note: 1. LVCMOS level input. Pull-down by internal resistor (100 k
).
Power-down Function Table
PDWN
L
H
IC Operating
Power-down
Active
OUTPUT
Low level
Clock signal output
Remark
Default *
1
Note: 1. All Circuits are set stand-by condition.
Clock Frequency Table
SEL
DIV2
Output Frequency
(IN:OUT Ratio)
54.0 to 72.0 MHz (1:2)
67.5 to 72.0 MHz (1:2.5)
27.0 to 36.0 MHz (1:1)
33.75 to 36.0 MHz(1:1.25)
Remark
L
H
L
H
L
L
H
H
Default
*
1
*
1
Note: 1. In case of selection of “SEL = H”, input frequency is limited 27 to 28.8 MHz.
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