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参数资料
| 型号： | RD74VT1G245CLE |
| 元件分类： | 总线收发器 |
| 英文描述： | 74V SERIES, 1-BIT TRANSCEIVER, TRUE OUTPUT, PBGA6 |
| 封装： | 0.90 X 1.40 MM, 0.50 MM HEIGHT, FBGA-6 |
| 文件页数： | 2/16页 |
| 文件大小： | 3510K |
| 代理商： | RD74VT1G245CLE |
RD74VT1G245
Rev.2.00 Apr. 01, 2005 page 8 of 13
Switching Characteristics (Cont.)
VCCA = 1.2 V
Ta = –40 to 85°C
VCCB=
1.2 V
VCCB=
1.5±0.1 V
VCCB=
1.8±0.15 V
VCCB=
2.5±0.2 V
VCCB=
3.3±0.3 V
Item
Symbol
From
(input)
To
(output)
Typ
Unit
Test
conditions
tPLH
10.5
8.0
6.4
4.7
4.0
tPHL
A
B
10.5
8.0
6.4
4.7
4.0
tPLH
10.5
10.0
9.8
9.5
9.1
Propagation
delay time
tPHL
B
A
10.5
10.0
9.8
9.5
9.1
ns CL = 15pF
RL = 2.0k
tHZ
8.0
tLZ
DIR
A
8.0
tHZ
13.5
10.5
9.5
7.5
Output
Disable time
tLZ
DIR
B
13.5
10.5
9.5
7.5
ns CL = 15pF
RL = 2.0k
tZH
*1
24.0
20.5
19.3
17.0
16.6
tZL
*1
DIR
A
24.0
20.5
19.3
17.0
16.6
tZH
*1
18.5
16.0
14.4
12.7
12.0
Output
Enable time
tZL
*1
DIR
B
18.5
16.0
14.4
12.7
12.0
ns CL = 15pF
RL = 2.0k
Note:
1. The enable time is a calculated value, derived using the formula shown in the section entitled enable times on
page 12.
Operating Characteristics
Ta = 25°C
Item
Symbol VCCA (V) VCCB (V) Min
Typ
Max
Unit
Test conditions
Power dissipation
capacitance
CPD
3.3
12
pF
f = 10 MHz
CL = 0
Power–up considerations
Level–translation devices offer an opportunity for successful mixed–voltage signal design.
A proper power–up sequence always should be followed to avoid excessive supply current, bus contention, oscillations,
or other anomalies caused by improperly biased device pins.
Take these precautions to guard against such power–up problems.
1.
Connect ground before any supply voltage is applied.
2.
Next, power up the control side of the device. (Power up of VCCA is first. Next power up is VCCB)
3.
Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, DIR low is needed (B data to A bus), ramp it with GND.
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