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| 型号： | RDC-19229-423W |
| 厂商： | DATA DEVICE CORP |
| 元件分类： | 位置变换器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, CQCC44 |
| 文件页数： | 5/24页 |
| 文件大小： | 256K |
| 代理商： | RDC-19229-423W |
13
Data Device Corporation
www.ddc-web.com
RDC-19220 SERIES
L-11/02-300
+S
-S
SIN
aR
R
+C
-C
COS
R
-
+
-
+
R
aR
C1
bR
2R
R
bR
+REF
-REF
R
C2
2 WIRE LVDT
REF IN
R
2 V
FS = 2 V
FIGURE 12A. 2-WIRE LVDT DIRECT INPUT
TABLE 7. LVDT OUTPUT CODE (14-BIT R/D OR
12-BIT LVDT)
LVDT OUTPUT
MSB
LSB
+ over full travel
+ full travel -1 LSB
+0.5 travel
+1 LSB
null
- 1 LSB
-0.5 travel
- full travel
- over full travel
01
xxxx
00
1111
00
1100
0000
00
1000
0000
0001
00
1000
0000
00
0111
1111
00
0100
0000
00
0000
11
xxxx
C1 = C2, set for phase lag = phase lead through the LVDT.
Note: TABLE 7 refers to FIGURE 12C.
Full Scale signal is in volts
α = signal to REF phase shift
An example of the magnitude of error is as follows:
Let: Quadrature Voltage = 11.8 mV
Let: F.S. signal = 11.8 V
Let:
α = 6°
Then: Magnitude of Error = 0.36 min @ 1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
specified by the synchro or resolver supplier plus the speed
voltage which is determined by the following formula:
Speed Voltage = (rotational speed/carrier frequency) F.S. signal
Where:
Speed Voltage is the quadrature due to rotation.
Rotation speed is the rps (rotations per second) of the synchro
or resolver.
Carrier frequency is the REF in Hz.
A circuit to LEAD or LAG the reference into the converter that will
compensate for phase-shift between the signal and the refer-
ence to reduce the effects of the quadrature is illustrated in FIG-
URE 11.
LVDT MODE
As shown in TABLE 1 the RDC-19220 Series units can be made
to operate as LVDT-to-digital converters by connecting
Resolution Control inputs A and B to “0,” “1,” or the -5 volt supply.
In this mode the RDC-19220 Series functions as a ratiometric
tracking linear converter. When linear ac inputs are applied from
a LVDT the converter operates over one quarter of its range. This
results in two less bits of resolution for LVDT mode than are pro-
vided in resolver mode.
FIGURE 12B shows a direct LVDT 2 Vrms full scale input. Some
LDVT output signals will need to be scaled to be compatible with
the converter input. FIGURE 12C is a schematic of an input scal-
ing circuit applicable to 3-wire LVDTs. The value of the scaling
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