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参数资料
| 型号： | REJ03F0023_M61140FP |
| 厂商： | Hitachi,Ltd. |
| 英文描述： | TUNER SINGLE CHIP |
| 中文描述： | 调谐器单芯片 |
| 文件页数： | 11/29页 |
| 文件大小： | 571K |
| 代理商： | REJ03F0023_M61140FP |
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M61140FP
Rev.1.2, Apr.16.2004, page 11 of 28
Pin No.
48
Pin name
EQ IN
Function
The video signal threw the SIF
trap is input to this terminal. DC
impression from pin 1 is required
for the input to 48 pins.
Circuit Diagram
33
48
100
Setting Data
M61140FP's bus format is based on Philips's I
2
C-bus.
Bidirectional bus communication control can be performed. It consists of WRITE mode which receives various data,
and READ mode which transmits data. Recognition in WRITE mode and READ mode is performed by specification of
the last bit on Address Byte (R/W bit). When the setup of a R/W bit is "0", it is set as WRITE mode and, in the case of
"1", is set as READ mode. Furthermore, it has the address in which four programs are possible.
It enables this to use two or more devices on the same I
2
C bus.
Moreover, four programmable addresses are possible. Therefore, two or more devices become usable on I
2
C bus.
A setup of an address is chosen by the voltage impressed to an address setting terminal (ADS:25 pin).
If the address Byte in agreement is received, a data line will be set to "L" between knowledge, and at the time of
WRITE mode, if Data Byte is received, SDA line between knowledge will be set to "L."
It shows a definition of bus protocol admitted in the following.
Mode_1 STA
CA DB1 DB2 CB1 CB2 STO
Mode_2 STA
CA CB1 CB2 DB1 DB2 STO
Mode_3 STA
CA DB1 DB2 STO
Mode_4 STA
CA CB1 CB2 STO
STA : Start condition
STO : Stop condition
CA : Chip address
DB1 : Divider data byte 1
DB2 : Divider data byte 2
CB1 : Control data byte 1
CB2 : Band data byte 2
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