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参数资料
| 型号： | REJ03F0023_M61140FP |
| 厂商： | Hitachi,Ltd. |
| 英文描述： | TUNER SINGLE CHIP |
| 中文描述： | 调谐器单芯片 |
| 文件页数： | 4/29页 |
| 文件大小： | 571K |
| 代理商： | REJ03F0023_M61140FP |
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M61140FP
Rev.1.2, Apr.16.2004, page 4 of 28
Pin Description
Pin No.
1
Pin name
VIDEO DET
OUT
Function
Video detected output terminal.
SIF trap and SIF B.P.F. are
connected to this terminal.
Because of open emitter
configuration, an externally
connected drive resistor is
necessary.
Circuit Diagram
1
33
50
2
Vreg
Regulated voltage output.
Approximately 3V output.
2
33
9.9K
6.2K
50
3
RF AGC
DELAY
RF AGC terminal. This terminal
combine 4.5MHz SIF signal
input with set up the RF AGC
delay point. The RF AGC delay
point is set up by the DC
component of input signal. AC
component is FM detection
threw the limiter amplifier.
3
33
5.1K
40p
40
43K
15p
4
44
IF AGC 2
IF AGC 1
IF AGC 2 terminal
IF AGC 2 terminal. External
capacitor effects AGC speed.
When this terminal is grounded,
the effect of VIF amp gain
becomes minimum.
44
4
33
50
10K
2.5K
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