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| 型号： | RFD14N05LSM9A |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | MOSFET N-CH 50V 14A TO-252AA |
| 产品培训模块： | High Voltage Switches for Power Processing |
| 产品目录绘图： | DPAK, TO-252(AA) |
| 标准包装： | 1 |
| FET 型： | MOSFET N 通道，金属氧化物 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 50V |
| 电流 - 连续漏极(Id) @ 25° C： | 14A |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 100 毫欧 @ 14A，5V |
| Id 时的 Vgs(th)（最大）： | 2V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 40nC @ 10V |
| 输入电容 (Ciss) @ Vds： | 670pF @ 25V |
| 功率 - 最大： | 48W |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-252-3，DPak（2 引线+接片），SC-63 |
| 供应商设备封装： | TO-252AA |
| 包装： | 标准包装 |
| 产品目录页面： | 1606 (CN2011-ZH PDF) |
| 其它名称： | RFD14N05LSM9ADKR |
RFD14N05L, RFD14N05LSM
Absolute Maximum Ratings
T C = 25 o C, Unless Otherwise Specified
RFD14N05L, RFD14N05LSM,
RFD14N05LSM9A
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V DSS
Drain to Gate Voltage (R GS = 20k ? ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . V DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V GS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I D
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P D
Derate above 25 o C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T J, T STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . T L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T pkg
50
50
± 10
14
Refer to Peak Current Curve
Refer to UIS Curve
48
0.32
-55 to 175
300
260
V
V
V
A
W
W/ o C
o C
o C
o C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T J = 25 o C to 150 o C.
Electrical Specifications
T C = 25 o C, Unless Otherwise Specified
PARAMETER
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
SYMBOL
BV DSS
V GS(TH)
I DSS
I GSS
r DS(ON)
t (ON)
t d(ON)
t r
t d(OFF)
t f
t (OFF)
TEST CONDITIONS
I D = 250 μ A, V GS = 0V, Figure 13
V GS = V DS , I D = 250 μ A, Figure12
V DS = 40V, V GS = 0V
V DS = 40V, V GS = 0V, T C = 150 o C
V GS = ± 10V
I D = 14A, V GS = 5V, Figures 9, 11
V DD = 25V, I D = 7A,
R L = 3.57 ? , V GS = 5V,
R GS = 0.6 ?
MIN
50
1
-
-
-
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
13
24
42
16
-
MAX
-
2
1
50
± 100
0.100
60
-
-
-
-
100
UNITS
V
V
μ A
μ A
nA
?
ns
ns
ns
ns
ns
ns
Total Gate Charge
Gate Charge at 5V
Q g(TOT)
Q g(5)
V GS = 0V to 10V
V GS = 0V to 5V
V DD = 40V, I D = 14A,
R L = 2.86 ?
Figures 20, 21
-
-
-
-
40
25
nC
nC
Threshold Gate Charge
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Q g(TH)
C ISS
C OSS
C RSS
R θ JC
R θ JA
R θ JA
V GS = 0V to 1V
V DS = 25V, V GS = 0V, f = 1MHz
Figure 14
TO-251
TO- 252
-
-
-
-
-
-
-
-
670
185
50
-
-
-
1.5
-
-
-
3.125
100
100
nC
pF
pF
pF
o C/W
o C/W
o C/W
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
SYMBOL
V SD
t rr
TEST CONDITIONS
I SD = 14A
I SD = 14A, dI SD /dt = 100A/ μ s
MIN
-
-
TYP
-
-
MAX
1.5
125
UNITS
V
ns
NOTES:
2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
?2004 Fairchild Semiconductor Corporation
RFD14N05L, RFD14N05LSM Rev. C0
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