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参数资料
| 型号： | RH80536GE0362M |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1860 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | FLIP CHIP, MICRO PGA-478 |
| 文件页数： | 5/30页 |
| 文件大小： | 887K |
| 代理商： | RH80536GE0362M |
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Datasheet
13
Low Power Features
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or
RESET#) are allowed on the FSB while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state by asserting the DPSLP# pin. (See Section 2.1.6.) While the processor is in the Sleep
state, the SLP# pin must be deasserted if another asynchronous FSB event needs to occur.
2.1.6
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped
during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings
on Intel 915PM/GM and Intel 915GMS/ICH6-M Express chipset-based platforms with the
CK410/CK410M clock chip are as follows:
Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. CK410/CK410M
will stop/tristate BCLK within 2 BCLKs +/- a few nanoseconds.
Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. CK410/CK410M
will drive BCLK to differential DC levels within 2 ~3 ns and starts toggling BCLK 2~6 BCLK
periods later.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-started after
DPSLP# de-assertion as described above. A period of 30 microseconds (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the FSB while the processor is in
Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant
state will result in unpredictable behavior.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop transactions.
2.1.7
Deeper Sleep State
The Deeper Sleep State is the lowest state power the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RH80536GE0362M S L7S9 | 制造商:Intel 功能描述:MPU Pentium |
| RH80536GE0412M | 制造商:Rochester Electronics LLC 功能描述:PENTIUM M 0.09 MICRON 533MHZ 1.102V 478FCBGA - Bulk |
| RH80536GE0412M S L7EJ | 制造商:Intel 功能描述:32-Bit Microprocessor |
| RH80536GE0412M S L7SM | 制造商:Intel 功能描述:MPU Pentium? M Processor 760 90nm 2GHz 1.05V 479-Pin uFCBGA |
| RH80536GE0412M S LJ8S | 制造商:Intel 功能描述:DOTHAN; MPU PENTIUM M 90NM 2GHZ 1.05V 479PIN UFCBGA - Trays |
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