参数资料
型号: RJ80530GZ004512
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1066 MHz, MICROPROCESSOR, PBGA479
封装: MICRO, FCBGA-479
文件页数: 32/96页
文件大小: 2018K
代理商: RJ80530GZ004512
Electrical Specifications
R
38
Mobile Intel
Pentium III Processor-M Datasheet
Table 20. System Bus Clock AC Specifications (133 MHz, Single Ended)
1
Symbol
Parameter
Min
Max
Unit
Figure
Notes
System Bus Frequency
133
MHz
T1S
BCLK Period
7.5
7.65
ns
6
Note 2
T1Sabs
BCLK Period – Instantaneous
Minimum
7.25
Note 2
T2S
BCLK Period Stability
±250
ps
Notes 2, 3, 4
T3S
BCLK High Time
1.4
ns
6
at>2.0V
T4S
BCLK Low Time
1.4
ns
6
at<0.5V
T5S
BCLK Rise Time
0.4
1.6
ns
6
Note 5
T6S
BCLK Fall Time
0.4
1.6
ns
6
Note 5
NOTES:
1.
All AC timings for GTL+ and CMOS signals are referenced to the BCLK rising edge at 1.25 V.
2.
Period, jitter, skew and offset measured at 1.25 V.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a
component of BCLK skew between devices.
5.
Measured between 0.5 V and 2.0 V.
Table 21. System Bus Clock AC Specifications (100 MHz, Single Ended)
1
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes
System Bus Frequency
100
MHz
T1S1
BCLK Period
10
ns
6
Note 2
T1S1abs BCLK Period – Instantaneous
Minimum
9.75
ns
Note 2
T2S1
BCLK Period Stability
±250
ps
Notes 2, 3, 4
T3S1
BCLK High Time
2.70
ns
6
at>2.0 V
T4S1
BCLK Low Time
2.45
ns
6
at<0.5 V
T5S1
BCLK Rise Time
0.4
1.6
ns
6
Note 5
T6S1
BCLK Fall Time
0.4
1.6
ns
6
Note 5
NOTES:
1.
All AC timings for AGTL and CMOS signals are referenced to the BCLK rising edge at 1.25 V.
2.
Period, jitter, skew and offset measured at 1.25 V.
3.
Not 100% tested. Specified by design/characterization.
4.
Measured on the rising edge of adjacent BCLKs at 1.25 V. The jitter present must be accounted for as a
component of BCLK skew between devices.
5.
Measured between 0.5 V and 2.0 V.
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