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参数资料
| 型号： | RK80530KZ006512 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1133 MHz, MICROPROCESSOR, CPGA370 |
| 封装： | FLIP CHIP, PGA-370 |
| 文件页数： | 16/94页 |
| 文件大小： | 1775K |
| 代理商： | RK80530KZ006512 |
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Datasheet
15
Intel Pentium III Processor with 512KB L2 Cache at 1.13GHz to 1.40GHz
2.7
Processor System Bus Unused Pins
All RESERVED pins must remain unconnected unless specifically noted. Connection of these pins
to VCCCORE, VREF, VSS, VTT or to any other signal (including each other) can result in component
malfunction or incompatibility with future processors. See Section 5.4 for a pin listing of the
processor and the location of each RESERVED pin.
PICCLK must be driven with a valid clock input and the PICD[1:0] signals must be pulled-up to
VCCCMOS1.5 even when the APIC will not be used. A separate pull-up resistor must be provided for
each PICD signal.
For reliable operation, always connect unused inputs or bidirectional signals to their deasserted
signal level. The pull-up or pull-down resistor values are system dependent and should be chosen
specifications of non-AGTL signals.
For unused AGTL inputs, the on-die termination will be sufficient. No external R
TT is necessary on
the motherboard
For unused CMOS inputs, active low signals should be connected through a pull-up resistor to
VCCCMOS1.5 and meet VIH requirements. Unused active high CMOS inputs should be connected
through a pull-down resistor to ground (VSS) and meet VIL requirements. Unused CMOS outputs
can be left unconnected. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system testability.
2.8
Processor System Bus Signal Groups
To simplify the following discussion, the processor system bus signals have been combined into
groups by buffer type. All P6 family processor system bus outputs are open drain and require a
high-level source provided termination resistors. However, the Intel Pentium III processor with
512KB L2 Cache includes on-die termination for AGTL signals and termination resistors placed on
the platform are not necessary except for the RESET# signal which still requires external
termination.
AGTL input signals have differential input buffers which use VREF as a reference signal. AGTL
output signals require termination to 1.25 V. In this document, the term “AGTL Input” refers to the
AGTL input group as well as the AGTL I/O group when receiving. Similarly, “AGTL Output”
refers to the AGTL output group as well as the AGTL I/O group when driving.
The PWRGOOD signal input is a 1.8V signal level and must be pulled up to VCCCMOS1.8. The
VTT_PWRGD is not 1.8V tolerant and must be connected to VTT (1.25V). Other CMOS inputs
(A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and STPCLK#) are
only 1.5 V tolerant and must be pulled up to VCCCMOS1.5. The CMOS, APIC, and TAP outputs are
open drain and must be pulled to the appropriate level to meet the input specifications of the
interfacing device.
The groups and the signals contained within each group are shown in Table 4. Refer to Section 7.0
for a description of these signals.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80530KZ012512 | 制造商:Intel 功能描述:MPU Pentium 制造商:Rochester Electronics LLC 功能描述:P3 (TUALATIN) 1.26GHZ 512 CACHE (FOR SERVERS) 133 FSB; 1.45V - Bulk |
| RK80530KZ012512S L5QL | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA2 |
| RK80530KZ012512S L6BX | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor-S 64-Bit 0.13um 1.26GHz 370-Pin FCPGA 制造商:Intel 功能描述:MPU PENTIUM III 64BIT 0.13UM 1.266GHZ 370PIN FCPGA2 - Trays |
| RK80530KZ017512 | 制造商:Rochester Electronics LLC 功能描述:P3 (TUALATIN) 1.4HZ 512 CACHE (FOR SERVERS) 133 FSB; 1.45V - Bulk |
| RK80530KZ017512S L5XL | 制造商:Intel 功能描述:32BIT MPU 80530KZ017512 1.40G |
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