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参数资料
| 型号： | RL5C478A |
| 厂商： | RICOH COMPANY LTD |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP256 |
| 封装： | 28 X 28 MM, 1.70 MM HEIGHT, 0.40 MM PITCH, PLASTIC, LQFP-256 |
| 文件页数： | 11/43页 |
| 文件大小： | 472K |
| 代理商： | RL5C478A |
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RL5C478A/RB5C478A
PCI-CARDBUS BRIDGE DATA SHEET
RICOH COMPANY,LTD.
12345 1998
REV 2.0
19
Pin Name
Type
Description
16-bit PC Card Interface Pin Descriptions (Continued)
ACD2#
BCD2#
IN
16-bit Card CARD DETECT 2: CD[2:1]# pins are used to detect the card insertion.
CD[2:1]# pins are used in conjunction with VS[2:1]# to decode card type information.
AVS1
BVS1
I/O
16-bit Card CARD VOLTAGE CAPABILITY SENSE 1: VS[2:1]# pins are used in
conjunction with CD[2:1] to decode card type information.
AVS2
BVS2
I/O
16-bit Card CARD VOLTAGE CAPABILITY SENSE 2: VS[2:1]# pins are used in
conjunction with CD[2:1]# to decode card type information.
3.7 CardBus PC Card Interface Signals
Pin Name
Type
Description
CardBus PC Card Interface Pin Descriptions
ACCLK
BCCLK
OUT(TS)
CardBus Clock: This signal provides timing for all transactions on the PC Card
Standard 95 interface and it is an input to every PC Card Standard 95 device. All other
CardBus PC Card signals, except CRST# (upon assertion), CCLKR, CCLKRUN#,
CINT#, CSTSCHG, CAUDIO, CCD[2:1]#, and CVS[2:1], are sampled on the rising
edge of CCLK, and all timing parameters are defined with respect to this edge.
ACCLKRUN#
BCCLKRUN#
I/O
s/h/z
CardBus Clock Run: This signal is used by cards to request starting (or speeding up)
clock ; CCLK. CCLKRUN# also indicates the clock status. For PC cards, CCLKRUN#
is an open drain output and it is also an input. The RL5C478A/RB5C478A indicates the
clock status of the primary bus to the CardBus card.
ACRST#
BCRST#
OUT(TS)
CardBus Card Reset: This signal is used to bring CardBus Card specific registers,
sequencers and signals to a consistent state. Anytime CRST# is asserted, all CardBus
card output signals will be driven to their begin state.
ACAD[31:0]
BCAD[31:0]
I/O
CardBus Address/Data: These signals are multiplexed on the same CardBus card
pins. A bus transaction consists of an address phase followed by one or more data
phases. CardBus card supports both read and write bursts. CAD[31:0] contain a
physical address (32 bits). For I/O, this is a byte address ; for configuration and
memory it is a DWORD address. During data phases, CAD[7:0] contain the east
significant byte(LSB) and CAD[31:24] contain the most significant byte(MSB). Write
data is stable and valid when CIRDY# is asserted and read data is stable and valid
when CTRDY# is asserted. Data is transferred during those clocks where both CIRDY#
and CTRDY# are asserted.
ACC/BE[3:0]#
BCC/BE[3:0]#
I/O
CardBus Command/Bye Enables: These signals are multiplexed on the same
CardBus card pins. During the address phase of a transaction, CC/BE[3:0]# define the
bus command. During the data phase, CC/BE[3:0]# are used as Byte Enables. The
Byte Enables are valid for the entire data phase and determine which byte lanes carry
meaningful data. CC/BE[0]# applies to byte 0 (LSB) and CC/BE[3]# applies to byte 3
(MSB).
ACPAR
BCPAR
I/O
CardBus Parity: This signal is even parity across CAD[31:0] and CC/BE[3:0]#. Parity
generation is required by all CardBus card agents. CPAR is stable and valid clock after
either CIRDY# is asserted on a write transaction or CTRDY# is asserted on a read
transaction. Once CPAR is valid, it remains valid until one clock after the completion of
the current data phase. (CPAR has the same timing as CAD[31:0] but delayed by one
clock.) The master drives CPAR for address and write data phases ; the target drives
CPAR for read data phases.
ACFRAME#
BCFRAME#
I/O
s/h/z
CardBus Cycle Frame: This signal is driven by the current master to indicate the
beginning and duration of a transaction. CFRAME# is asserted to indicate that a bus
transaction is beginning. While CFRAME# is asserted, data transfers continue. When
CFRAME# is deasserted, the transaction is in the final data phase.
ACIRDY#
BCIRDY#
I/O
s/h/z
CardBus Initiator Ready: This signal indicates the initiating agent‘s(bus master’s)
ability to complete the current data phase of the transaction. CIRDY# is used in
conjunction with CTRDY#. A data phase is completed on any clock both CIRDY# and
CTRDY# are sampled asserted. During a write, CIRDY# indicates that valid data is
present on CAD[31:0]. During a read, it indicates the master is prepared to accept
data. Wait cycles are inserted until both CIRDY# and CTRDY# are asserted together.
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