参数资料
型号: RS5C317B-E1
厂商: RICOH COMPANY LTD
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO14
封装: 0.65 MM PITCH, SSOP-14
文件页数: 19/40页
文件大小: 347K
代理商: RS5C317B-E1
RS5C317A/B
22
Considerations in Use of XSTP Bit
7. Oscillator Halt Sensing
Oscillation Halt can be sensed through monitoring the XSTP bit with preceding setting of the XSTP bit to 0 by
writing any data to the control register 1. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This
function can be applied to judge clock data validity.
When the XSTP bit is set to 1, the timer register bits and CLEN bit perform as follows:
CLEN=0
TM3=TM2=TM1=TMCL=0 (Timer halts)
*1) While the CE pin is held at the low level, the XSTP bit is set to 1 upon power-on from 0V.
Note that any instantaneous power disconnection may cause operational failure. When the CE pin is held at the high level, oscillation halt is not
sensed and the value of the XSTP bit when the CE pin is held at the low level is retained.
*2) Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted.
Ensure error-free oscillation halt sensing by preventing the following:
1) Instantaneous disconnection of VDD
2) Condensation on the crystal oscillator
3) Generation of noise on the PCB in the crystal oscillator
4) Application of voltage exceeding prescribed maximum ratings to the individual pins of the IC
Power-on from 0V
*1
XSTP
Oscillation halt
Writing of data to
control register 1
(in the presence of oscillation)
Oscillation restart
*2
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