参数资料
型号: RS5C317B-E1
厂商: RICOH COMPANY LTD
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO14
封装: 0.65 MM PITCH, SSOP-14
文件页数: 9/40页
文件大小: 347K
代理商: RS5C317B-E1
RS5C317A/B
13
2.5 Timer register (BANK 1, at 9h)
Cycle time setting table for the time counter (The “*” mark indicates 0 or 1.)
D3
D2
D1
D0
TM3
TM2
TM1
TMCL
(For read/write)
Clock Frequency Selection Bit for the Timer Counter *1
Period Selection Bit for the Timer Counter *2
TMCL
Description
0
1
Clock frequency=512Hz (1.953ms)
Clock frequency=16Hz (62.5ms)
TM3
TM2
TM1
TMCL
T1 (cycle time for
T2 (time between setting
T3 (cycle time for
watch-dog-timer) *3
TMR=1 and TMOUT output) *4
free-run timer) *5
0
*
Timer halts
0
1
0
1.953ms
1.953 to 3.907ms
3.906ms
0
1
0
5.859ms
5.859 to 7.813ms
7.812ms
0
1
0
9.765ms
9.765 to 11.72ms
11.719ms
1
0
13.67ms
13.67 to 15.63ms
15.625ms
1
0
1
0
17.57ms
17.57 to 19.54ms
19.531ms
1
0
21.48ms
21.48 to 23.44ms
23.437ms
1
0
25.39ms
25.39 to 27.35ms
27.344ms
0
1
62.5ms
62.5 to 125ms
125ms
0
1
0
1
187.5ms
187.5 to 250ms
250ms
0
1
312.5ms
312.5 to 375ms
375ms
1
0
1
437.5ms
437.5 to 500ms
500ms
1
0
1
562.5ms
562.5 to 625ms
625ms
1
0
1
687.5ms
687.5 to 750ms
750ms
1
812.5ms
812.5 to 875ms
875ms
*1) (TMCL)
“512Hz” and “16Hz” are selectively available. When the “XSTP” bit is set to 1, the “TMCL” bit is automatically set to 0. There may be possibility to be
ahead or behind of the clock counter at maximum of a halt of clock frequency (512Hz or 16Hz), when the “ADJ” bit is set to 1 in the control register-1.
*2) (TM3-TM1)
When the “XSTP” bit is set to 1 the “TM3, TM2”, and “TM1” is automatically set to 0, the timer counter halts.
*3) T1: The maximum disable time for timer output, TMOUT=L, after setting the “TMR” bit to 1.
*4) T2: Time between timer output and setting the “TMR” bit to 1, or setting the timer register to any value.
*5) T3: Timer output cycle time without setting “TMR” bit to 1, cycle time for free-run-timer.
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