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ETM21E-02
13.1.9. Control Register ( Reg
0F [h] )
Address [h]
Function
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
F
Control Register
TEST3
TIE
AIE
STOP
This is a flag register that indicates circumstantial results, such as the state of power supply, the generated state
of various interrupt events, the reliability of internal data, and the like.
1) TEST3 bit
This bits is the manufacturer's test bit.
Always leave this bit value as "0" except when testing.
Be careful to avoid writing to this bit when writing "1" to other bits in this register.
The three TEST* bits are undefined when read. Those bits should be masked after being read.
2) TIE bit ( Timer Interrupt Enable )
This bit sets the operation of the /IRQ interrupt signal when a fixed-cycle interrupt event has occurred (the
TF bit value changes from "0" to "1").
When a "1" is written to this bit, occurrence of an interrupt event causes a low-level interrupt signal to be
output from /IRQ pin.
Writing "0" to this bit prohibits low-level output from the /IRQ pin.
For details, see "13.2. Fixed-cycle Timer Interrupt Function ".
3) AIE bit ( Alarm Interrupt Enable )
This bit sets the operation of the /IRQ interrupt signal when an alarm interrupt event has occurred (the AF
bit value changes from "0" to "1").
When a "1" is written to this bit, occurrence of an interrupt event causes a low-level interrupt signal to be
output from /IRQ pin.
Writing "0" to this bit prohibits low-level output from the /IRQ pin.
For details, see "13.4. Alarm Interrupt Function".
4) STOP bit
This bit is used to stop functions related to the RTC's internal counter operations.
Writing a "1" to this bit stops the counter operations.
Writing a "0" to this bit cancels stop status (restarts counter operations).
For optimum performance, do not use this bit for functions other than the clock and calendar functions.