
RX
4571 SA
Page - 12
ETM21E-02
12.2. Register table
Address
Function
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
note
0
SEC
40
20
10
8
4
2
1
3
1
MIN
40
20
10
8
4
2
1
3
2
HOUR
20
10
8
4
2
1
3
WEEK
6
5
4
3
2
1
0
3
4
DAY
20
10
8
4
2
1
3
5
MONTH
10
8
4
2
1
3
6
YEAR
80
40
20
10
8
4
2
1
7
RAM
4
8
MIN Alarm
AE
40
20
10
8
4
2
1
9
HOUR Alarm
AE
20
10
8
4
2
1
4
DAY Alarm
6
5
4
3
2
1
0
A
DAY Alarm
AE
20
10
8
4
2
1
4
B
Timer Counter 0
128
64
32
16
8
4
2
1
C
Timer Counter 1
2048
1024
512
256
4
D
Extension Register
TEST1
WADA
TE
FSEL1 FSEL0 TSEL1 TSEL0
1, 3
E
Flag Register
TEST2
TF
AF
VLF
RSV
1, 3, 5
F
Control Register
TEST3
TIE
AIE
STOP
3
Note
During the initial power-on (from 0 V) and if the value of the VLF bit is "1" when the VLF bit is read, be sure to
initialize all registers before using them.
When doing this, be careful to avoid setting incorrect data as the date or time, as timed operations cannot be
guaranteed if incorrect date or time data has been set.
1.
During the initial power-on (from 0 V), the power-on reset function sets "1" to the VLF bit.
Since the value of other registers is undefined at this time, be sure to reset all registers before using them.
2.
The TEST1, TEST2, TEST3 bits are Epson Toyocom test bits.
Be sure to write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing.
The four TEST* bits are undefined when read. Those bits should be masked after being read.
3.
The ' ' mark indicates a write-prohibited bit, which returns a "0" when read.
4.
The '
' mark indicates a read/write-accessible RAM bit for any data.
5.
The RSV bit are Epson Toyocom test bits.
Be sure to write "0" by initializing before using the clock module. Afterward, be sure to set "0" when writing.
The four RSV bits are undefined when read. Those bits should be masked after being read.