![](http://datasheet.mmic.net.cn/120000/S1C17651D00E10P_datasheet_3574359/S1C17651D00E10P_106.png)
12 16-BIT PWM TIMER (T16A2)
S1C17651 TECHNICAL MANUAL
Seiko Epson Corporation
12-17
In capture mode (CCBMD = 1)
When the counter value is captured at the external trigger signal (CAPBx) edge selected using CAPB-
TRG[1:0]/T16A_CCCTLx register, the captured value is loaded to this register. At the same time a
capture B interrupt can be generated, thus the captured counter value can be read out in the interrupt
handler.
T16A Comparator/Capture Ch.x Interrupt Enable Register (T16A_IENx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A
Comparator/
Capture Ch.x
Interrupt Enable
Register
(T16A_IENx)
0x540a
(16 bits)
D15–6 –
reserved
–
0 when being read.
D5
CAPBOWIE Capture B overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D4
CAPAOWIE Capture A overwrite interrupt enable 1 Enable
0 Disable
0
R/W
D3
CAPBIE
Capture B interrupt enable
1 Enable
0 Disable
0
R/W
D2
CAPAIE
Capture A interrupt enable
1 Enable
0 Disable
0
R/W
D1
CBIE
Compare B interrupt enable
1 Enable
0 Disable
0
R/W
D0
CAIE
Compare A interrupt enable
1 Enable
0 Disable
0
R/W
D[15:6]
Reserved
D5
CAPBOWIE: Capture B Overwrite Interrupt Enable Bit
Enables or disables capture B overwrite interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CAPBOWIE to 1 enables capture B overwrite interrupt requests to the ITC. Setting it to 0 dis-
ables interrupts.
D4
CAPAOWIE: Capture A Overwrite Interrupt Enable Bit
Enables or disables capture A overwrite interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CAPAOWIE to 1 enables capture A overwrite interrupt requests to the ITC. Setting it to 0 dis-
ables interrupts.
D3
CAPBIE: Capture B Interrupt Enable Bit
Enables or disables capture B interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CAPBIE to 1 enables capture B interrupt requests to the ITC. Setting it to 0 disables interrupts.
D2
CAPAIE: Capture A Interrupt Enable Bit
Enables or disables capture A interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CAPAIE to 1 enables capture A interrupt requests to the ITC. Setting it to 0 disables interrupts.
D1
CBIE: Compare B Interrupt Enable Bit
Enables or disables compare B interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CBIE to 1 enables compare B interrupt requests to the ITC. Setting it to 0 disables interrupts.
D0
CAIE: Compare A Interrupt Enable Bit
Enables or disables compare A interrupts.
1 (R/W): Interrupt enabled
0 (R/W): Interrupt disabled (default)
Setting CAIE to 1 enables compare A interrupt requests to the ITC. Setting it to 0 disables interrupts.