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| 型号： | S1C60N05D0A0100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, UUC53 |
| 封装： | DIE-53 |
| 文件页数： | 8/95页 |
| 文件大小： | 736K |
| 代理商： | S1C60N05D0A0100 |
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9.3
Block Diagram
Figure 9-1 presents the SAU integrated in an example system with a CPU, some memories,
some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB) and
the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory
accesses are done via the HSB. The SAU receives an access on its HSB slave interface,
remaps it, checks that the channel is unlocked, and if so, initiates a transfer on its HSB master
interface to the remapped address.
The thin arrows in Figure 9-1 exemplifies control flow when using the SAU. The CPU wants to
read the RX Buffer in the USART. The MPU has been configured to protect all registers in the
USART from user mode access, while the SAU has been configured to remap the RX Buffer into
a memory space that is not protected by the MPU. This unprotected memory space is mapped
into the SAU HSB slave space. When the CPU reads the appropriate address in the SAU, the
SAU will perform an access to the desired RX buffer register in the USART, and thereafter return
the read results to the CPU. The return data flow will follow the opposite direction of the control
flow arrows in Figure 9-1.
Figure 9-1.
SAU Block Diagram
SAU Channel
Bus master
MPU
CPU
Bus slave
USART
PWM
Bus slave
Bus master
Bus slave
Flash
Bus slave
RAM
Bus bridge
SAU Configuration
Interrupt
request
High Speed Bus
SAU
P
er
iph
er
a
lB
u
s
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