- 您现在的位置：买卖IC网 > PDF目录25640 > S1C60N05D0A0100 MICROCONTROLLER, UUC53 PDF资料下载
参数资料
| 型号： | S1C60N05D0A0100 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, UUC53 |
| 封装： | DIE-53 |
| 文件页数： | 9/95页 |
| 文件大小： | 736K |
| 代理商： | S1C60N05D0A0100 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页
106
32145C–06/2013
AT32UC3L0128/256
9.4
Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
9.4.1
Power Management
If the CPU enters a sleep mode that disables clocks used by the SAU, the SAU will stop func-
tioning and resume operation after the system wakes up from sleep mode.
9.4.2
Clocks
The SAU has two bus clocks connected: One High Speed Bus clock (CLK_SAU_HSB) and one
Peripheral Bus clock (CLK_SAU_PB). These clocks are generated by the Power Manager. Both
clocks are enabled at reset, and can be disabled by writing to the Power Manager. The user has
to ensure that CLK_SAU_HSB is not turned off before accessing the SAU. Likewise, the user
must ensure that no bus access is pending in the SAU before disabling CLK_SAU_HSB. Failing
to do so may deadlock the High Speed Bus.
9.4.3
Interrupt
The SAU interrupt request line is connected to the interrupt controller. Using the SAU interrupt
requires the interrupt controller to be programmed first.
9.4.4
Debug Operation
When an external debugger forces the CPU into debug mode, the SAU continues normal opera-
tion. If the SAU is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
9.5
Functional Description
9.5.1
Enabling the SAU
The SAU is enabled by writing a one to the Enable (EN) bit in the Control Register (CR). This will
set the SAU Enabled (EN) bit in the Status Register (SR).
9.5.2
Configuring the SAU Channels
The SAU has a set of channels, mapped in the HSB memory space. These channels can be
configured by a Remap Target Register (RTR), located at the same memory address. When the
SAU is in normal mode, the SAU channel is addressed, and when the SAU is in setup mode, the
RTR can be addressed.
Before the SAU can be used, the channels must be configured and enabled. To configure a
channel, the corresponding RTR must be programmed with the Remap Target Address. To do
this, make sure the SAU is in setup mode by writing a one to the Setup Mode Enable (SEN) bit
in CR. This makes sure that a write to the RTR address accesses the RTR, not the SAU chan-
nel. Thereafter, the RTR is written with the address to remap to, typically the address of a
specific PB register. When all channels have been configured, return to normal mode by writing
a one to the Setup Mode Disable (SDIS) in CR. The channels can now be enabled by writing
ones to the corresponding bits in the Channel Enable Registers (CERH/L).
The SAU is only able to remap addresses above 0xFFFC0000.
相关PDF资料 |
PDF描述 |
|---|---|
| S1C621A0F0A0100 | MICROCONTROLLER, PQFP80 |
| S1C63158D0A010P | 4-BIT, FLASH, 4 MHz, MICROCONTROLLER, UUC53 |
| S1C7XXXF00E199 | 16-BIT, 90 MHz, RISC MICROCONTROLLER, PQFP |
| S2041 | PHOTO TRANSISTOR DETECTOR |
| S3P44R10 | TRIGGER OUTPUT SOLID STATE RELAY, 4000 V ISOLATION-MAX |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S1C60N08 | 制造商:EPSON 制造商全称:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60N16 | 制造商:EPSON 制造商全称:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C60R08 | 制造商:EPSON 制造商全称:EPSON 功能描述:4-bit Single Chip Microcomputer |
| S1C63004 | 制造商:EPSON 制造商全称:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
| S1C63008 | 制造商:EPSON 制造商全称:EPSON 功能描述:CMOS 4-bit Single Chip Microcontroller |
发布紧急采购，3分钟左右您将得到回复。